From 423d01a1b367d82a3855972483530968309cbbd4 Mon Sep 17 00:00:00 2001 From: Daisuke Matsushita Date: Tue, 21 Mar 2017 15:05:15 +0900 Subject: [PATCH] board: renesas: Add V3M Eagle board V3M Eagle is a board based on R-Car V3M SoC (R8A7797) Signed-off-by: Vladimir Barinov --- arch/arm/cpu/armv8/Kconfig | 4 + board/renesas/eagle/Kconfig | 15 +++ board/renesas/eagle/MAINTAINERS | 6 + board/renesas/eagle/Makefile | 9 ++ board/renesas/eagle/eagle.c | 252 ++++++++++++++++++++++++++++++++++++++++ configs/r8a7797_eagle_defconfig | 9 ++ include/configs/r8a7797_eagle.h | 152 ++++++++++++++++++++++++ 7 files changed, 447 insertions(+) create mode 100644 board/renesas/eagle/Kconfig create mode 100644 board/renesas/eagle/MAINTAINERS create mode 100644 board/renesas/eagle/Makefile create mode 100644 board/renesas/eagle/eagle.c create mode 100644 configs/r8a7797_eagle_defconfig create mode 100644 include/configs/r8a7797_eagle.h diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index dfd9bab..c857214 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -16,6 +16,9 @@ config TARGET_SALVATOR_X config TARGET_ULCB bool "ULCB board" +config TARGET_EAGLE + bool "EAGLE board" + endchoice config R8A7796X @@ -45,5 +48,6 @@ config SYS_SOC source "board/renesas/salvator-x/Kconfig" source "board/renesas/ulcb/Kconfig" +source "board/renesas/eagle/Kconfig" endif diff --git a/board/renesas/eagle/Kconfig b/board/renesas/eagle/Kconfig new file mode 100644 index 0000000..dffbbeb --- /dev/null +++ b/board/renesas/eagle/Kconfig @@ -0,0 +1,15 @@ +if TARGET_EAGLE + +config SYS_SOC + default "rcar_gen3" + +config SYS_BOARD + default "eagle" + +config SYS_VENDOR + default "renesas" + +config SYS_CONFIG_NAME + default "r8a7797_eagle" if R8A7797 + +endif diff --git a/board/renesas/eagle/MAINTAINERS b/board/renesas/eagle/MAINTAINERS new file mode 100644 index 0000000..c411373 --- /dev/null +++ b/board/renesas/eagle/MAINTAINERS @@ -0,0 +1,6 @@ +EAGLE BOARD +M: foo +S: Maintained +F: board/renesas/eagle/ +F: include/configs/r8a7797_eagle.h +F: configs/r8a7797_eagle_defconfig diff --git a/board/renesas/eagle/Makefile b/board/renesas/eagle/Makefile new file mode 100644 index 0000000..87d63e1 --- /dev/null +++ b/board/renesas/eagle/Makefile @@ -0,0 +1,9 @@ +# +# board/renesas/eagle/Makefile +# +# Copyright (C) 2016 Renesas Electronics Corporation +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := eagle.o ../rcar-gen3-common/common.o diff --git a/board/renesas/eagle/eagle.c b/board/renesas/eagle/eagle.c new file mode 100644 index 0000000..48ea727 --- /dev/null +++ b/board/renesas/eagle/eagle.c @@ -0,0 +1,252 @@ +/* + * board/renesas/eagle/eagle.c + * This file is Eagle board support. + * + * Copyright (C) 2016 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +#define SCIF0_MSTP207 (1 << 7) +#define SD0_MSTP314 (1 << 14) +#define ETHERAVB_MSTP812 (1 << 12) +#define RPC_MSTP917 (1 << 17) +#define I2C0_MSTP931 (1 << 31) + +#define SD0CKCR 0xE6150074 + +#define PFC_PMMR 0xe6060000 +#define PFC_POC1 0xe6060384 +#define POC_MMC_3V3 0x003ff000 + +void s_init(void) +{ + struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; + struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; + + /* Watchdog init */ + writel(0xA5A5A500, &rwdt->rwtcsra); + writel(0xA5A5A500, &swdt->swtcsra); +} + +int board_early_init_f(void) +{ + int freq; + + rcar_prr_init(); + + writel(0xa5a5ffff, 0xe6150900); + writel(0x5a5a0000, 0xe6150904); + mstp_clrbits_le32(MSTPSR1, SMSTPCR1, 0x02000000); + /* SCIF0 */ + mstp_clrbits_le32(MSTPSR2, SMSTPCR2, SCIF0_MSTP207); + /* SDHI2/MMC */ + mstp_clrbits_le32(MSTPSR3, SMSTPCR3, SD0_MSTP314); + /* EHTERAVB */ + mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHERAVB_MSTP812); + /* QSPI */ + mstp_clrbits_le32(MSTPSR9, SMSTPCR9, RPC_MSTP917); + /* I2C0 */ + mstp_clrbits_le32(MSTPSR9, SMSTPCR9, I2C0_MSTP931); + + freq = rcar_get_sdhi_config_clk(); + writel(freq, SD0CKCR); + + return 0; +} + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x50000; + + /* Init PFC controller */ + pinmux_init(); + +#ifdef CONFIG_RAVB + /* GPSR1 */ + gpio_request(GPIO_GFN_AVB0_AVTP_CAPTURE, NULL); + gpio_request(GPIO_FN_AVB0_AVTP_MATCH, NULL); + gpio_request(GPIO_FN_AVB0_LINK, NULL); + gpio_request(GPIO_FN_AVB0_PHY_INT, NULL); + /* gpio_request(GPIO_FN_AVB0_MAGIC, NULL); */ + gpio_request(GPIO_FN_AVB0_MDC, NULL); + gpio_request(GPIO_FN_AVB0_MDIO, NULL); + gpio_request(GPIO_FN_AVB0_TXCREFCLK, NULL); + gpio_request(GPIO_FN_AVB0_TD3, NULL); + gpio_request(GPIO_FN_AVB0_TD2, NULL); + gpio_request(GPIO_FN_AVB0_TD1, NULL); + gpio_request(GPIO_FN_AVB0_TD0, NULL); + gpio_request(GPIO_FN_AVB0_TXC, NULL); + gpio_request(GPIO_FN_AVB0_TX_CTL, NULL); + gpio_request(GPIO_FN_AVB0_RD3, NULL); + gpio_request(GPIO_FN_AVB0_RD2, NULL); + gpio_request(GPIO_FN_AVB0_RD1, NULL); + gpio_request(GPIO_FN_AVB0_RD0, NULL); + gpio_request(GPIO_FN_AVB0_RXC, NULL); + gpio_request(GPIO_FN_AVB0_RX_CTL, NULL); + + /* IPSR7 */ + gpio_request(GPIO_IFN_AVB0_AVTP_CAPTURE, NULL); + /* IPSR3 */ + gpio_request(GPIO_FN_AVB0_AVTP_PPS, NULL); + + /* AVB_PHY_RST */ + gpio_request(GPIO_GP_1_16, NULL); + gpio_direction_output(GPIO_GP_1_16, 0); + mdelay(20); + gpio_set_value(GPIO_GP_1_16, 1); + udelay(1); +#endif + +#if !defined(CONFIG_SYS_NO_FLASH) + /* QSPI */ + gpio_request(GPIO_FN_QSPI0_SPCLK, NULL); + gpio_request(GPIO_FN_QSPI0_MOSI_IO0, NULL); + gpio_request(GPIO_FN_QSPI0_MISO_IO1, NULL); + gpio_request(GPIO_FN_QSPI0_IO2, NULL); + gpio_request(GPIO_FN_QSPI0_IO3, NULL); + gpio_request(GPIO_FN_QSPI0_SSL, NULL); + gpio_request(GPIO_FN_QSPI1_SPCLK, NULL); + gpio_request(GPIO_FN_QSPI1_MOSI_IO0, NULL); + gpio_request(GPIO_FN_QSPI1_MISO_IO1, NULL); + gpio_request(GPIO_FN_QSPI1_IO2, NULL); + gpio_request(GPIO_FN_QSPI1_IO3, NULL); + gpio_request(GPIO_FN_QSPI1_SSL, NULL); + gpio_request(GPIO_FN_RPC_RESET_N, NULL); + gpio_request(GPIO_FN_RPC_WP_N, NULL); + gpio_request(GPIO_FN_RPC_INT_N, NULL); +#endif + +#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_RCAR) + /* I2C0 to access PMIC */ + gpio_request(GPIO_IFN_SDA0, NULL); + gpio_request(GPIO_IFN_SCL0, NULL); +#endif + return 0; +} + +#define MAHR 0xE68005C0 +#define MALR 0xE68005C8 +int board_eth_init(bd_t *bis) +{ + int ret = -ENODEV; + u32 val; + unsigned char enetaddr[6]; + + if (!eth_getenv_enetaddr("ethaddr", enetaddr)) + return ret; + + /* Set Mac address */ + val = enetaddr[0] << 24 | enetaddr[1] << 16 | + enetaddr[2] << 8 | enetaddr[3]; + writel(val, MAHR); + + val = enetaddr[4] << 8 | enetaddr[5]; + writel(val, MALR); + +#ifdef CONFIG_RAVB + ret = ravb_initialize(bis); +#endif + return ret; +} + +/* Salvator-X has KSZ9031RNX */ +/* Tri-color dual-LED mode(Pin 41 pull-down) */ +int board_phy_config(struct phy_device *phydev) +{ + /* hardware use default(Tri-color:0) setting. */ + + return 0; +} + +int board_mmc_init(bd_t *bis) +{ + int ret = -ENODEV; +#ifdef CONFIG_SH_SDHI + u32 val; + + /* SDHI2/eMMC */ + gpio_request(GPIO_FN_MMC_D0, NULL); + gpio_request(GPIO_FN_MMC_D1, NULL); + gpio_request(GPIO_FN_MMC_D2, NULL); + gpio_request(GPIO_FN_MMC_D3, NULL); + gpio_request(GPIO_FN_MMC_D4, NULL); + gpio_request(GPIO_FN_MMC_D5, NULL); + gpio_request(GPIO_FN_MMC_D6, NULL); + gpio_request(GPIO_FN_MMC_D7, NULL); + gpio_request(GPIO_FN_MMC_CLK, NULL); + gpio_request(GPIO_FN_MMC_CMD, NULL); + gpio_request(GPIO_FN_MMC_CD, NULL); + gpio_request(GPIO_FN_MMC_WP, NULL); + + val = readl(PFC_POC1); + val &= ~POC_MMC_3V3; /* POC = 1.8V */ + writel(~val, PFC_PMMR); + writel(val, PFC_POC1); + + ret = sh_sdhi_init(CONFIG_SYS_SH_SDHI2_BASE, 0, + SH_SDHI_QUIRK_64BIT_BUF); +#endif + return ret; +} + + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_1_SIZE; + + return 0; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; +} + +const struct rcar_sysinfo sysinfo = { + CONFIG_RCAR_BOARD_STRING +}; + +void reset_cpu(ulong addr) +{ +#if defined(CONFIG_SYS_I2C) && defined(CONFIG_SYS_I2C_RCAR) + u8 val; + + i2c_set_bus_num(0); + i2c_init(400000, 0); + i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); + val |= 0x02; + i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); +#endif +} + +#if defined(CONFIG_DISPLAY_BOARDINFO) +int checkboard(void) +{ + printf("Board: %s\n", sysinfo.board_string); + return 0; +} +#endif diff --git a/configs/r8a7797_eagle_defconfig b/configs/r8a7797_eagle_defconfig new file mode 100644 index 0000000..d68e28f --- /dev/null +++ b/configs/r8a7797_eagle_defconfig @@ -0,0 +1,9 @@ +CONFIG_ARM=y +CONFIG_RCAR_GEN3=y +CONFIG_DM_SERIAL=y +CONFIG_TARGET_EAGLE=y +CONFIG_R8A7797=y +CONFIG_SPL=y +CONFIG_SH_SDHI=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_SPANSION=y diff --git a/include/configs/r8a7797_eagle.h b/include/configs/r8a7797_eagle.h new file mode 100644 index 0000000..c6ab5b7 --- /dev/null +++ b/include/configs/r8a7797_eagle.h @@ -0,0 +1,152 @@ +/* + * include/configs/eagle.h + * This file is eagle board configuration. + * CPU r8a7797. + * + * Copyright (C) 2016 Renesas Electronics Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __EAGLE_H +#define __EAGLE_H + +#undef DEBUG +#define CONFIG_RCAR_BOARD_STRING "R-Car EAGLE" +#define CONFIG_RCAR_TARGET_STRING "r8a7797" + +#include "rcar-gen3-common.h" + +/* Cache Definitions */ +//#define CONFIG_SYS_DCACHE_OFF +//#define CONFIG_SYS_ICACHE_OFF + +/* SCIF */ +#define CONFIG_SCIF_CONSOLE +#define CONFIG_CONS_SCIF0 +#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_S3D4_CLK_FREQ + +/* [A] Hyper Flash */ +/* use to RPC(SPI Multi I/O Bus Controller) */ + + /* underconstruction */ + +#define CONFIG_SYS_NO_FLASH +#if defined(CONFIG_SYS_NO_FLASH) +#define CONFIG_SPI +#define CONFIG_RCAR_GEN3_QSPI +#define CONFIG_SH_QSPI_BASE 0xEE200000 +#define CONFIG_CMD_SF +#define CONFIG_CMD_SPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SPANSION +#else +#undef CONFIG_CMD_SF +#undef CONFIG_CMD_SPI +#undef CONFIG_SPI_FLASH +#undef CONFIG_SPI_FLASH_SPANSION +#endif + +/* Ethernet RAVB */ +#define CONFIG_RAVB +#define CONFIG_RAVB_PHY_ADDR 0x0 +#define CONFIG_RAVB_PHY_MODE PHY_INTERFACE_MODE_RGMII_ID +#define CONFIG_NET_MULTI +#define CONFIG_PHYLIB +#define CONFIG_PHY_MICREL +#define CONFIG_BITBANGMII +#define CONFIG_BITBANGMII_MULTI +#define CONFIG_SH_ETHER_BITBANG + +/* Board Clock */ +/* XTAL_CLK : 33.33MHz */ +#define RCAR_XTAL_CLK 33333333u +#define CONFIG_SYS_CLK_FREQ RCAR_XTAL_CLK +/* ch0to2 CPclk, ch3to11 S3D2_PEREclk, ch12to14 S3D2_RTclk */ +/* CPclk 16.66MHz, S3D2 133.33MHz , S3D4 66.66MHz */ +#define CONFIG_CP_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2) +#define CONFIG_PLL1_CLK_FREQ (CONFIG_SYS_CLK_FREQ * 192 / 2) +#define CONFIG_S3D2_CLK_FREQ (266666666u/2) +#define CONFIG_S3D4_CLK_FREQ (266666666u/4) +#define CONFIG_S2D2_CLK_FREQ (133333333u) + +/* Generic Timer Definitions (use in assembler source) */ +#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */ + +/* Generic Interrupt Controller Definitions */ +#define GICD_BASE (0xF1010000) +#define GICC_BASE (0xF1020000) +#define CONFIG_GICV2 + +/* i2c */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_RCAR +#define CONFIG_SYS_RCAR_I2C0_SPEED 400000 +#define CONFIG_SYS_RCAR_I2C1_SPEED 400000 +#define CONFIG_SYS_RCAR_I2C2_SPEED 400000 +#define CONFIG_SYS_RCAR_I2C3_SPEED 400000 +#define CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS 4 +#define CONFIG_SYS_I2C_POWERIC_ADDR 0x5A +#define CONFIG_HP_CLK_FREQ CONFIG_S2D2_CLK_FREQ + +/* USB */ +#undef CONFIG_CMD_USB + +/* Module clock supply/stop status bits */ +/* MFIS */ +#define CONFIG_SMSTP2_ENA 0x00002000 +/* serial(SCIF0) */ +#define CONFIG_SMSTP3_ENA 0x00000400 +/* INTC-AP, INTC-EX */ +#define CONFIG_SMSTP4_ENA 0x00000180 + +/* SDHI */ +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_SH_SDHI_FREQ 200000000 +#define CONFIG_SH_SDHI_MMC + +#define CONFIG_SH_MMCIF +#define CONFIG_SH_MMCIF_ADDR 0xee140000 +#define CONFIG_SH_MMCIF_CLK (CONFIG_SH_SDHI_FREQ) + +/* Environment */ +#define CONFIG_ENV_IS_IN_SPI_FLASH + +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_SECT_SIZE (256 * 1024) +#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) + +/* Environment in eMMC, at the end of 2nd "boot sector" */ +#if defined(CONFIG_ENV_IS_IN_MMC) +#define CONFIG_ENV_OFFSET (-CONFIG_ENV_SIZE) +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_SYS_MMC_ENV_PART 2 +#define CONFIG_GENERIC_MMC + +#elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) +/* Environment in QSPI */ +#define CONFIG_ENV_ADDR 0x700000 +#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR) + +#else +/* Unused Environment */ +#define CONFIG_ENV_IS_NOWHERE +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0xffffffffffffffff\0" \ + "initrd_high=0xffffffffffffffff\0" \ + "ethact=ravb\0" + +#define CONFIG_BOOTARGS \ + "root=/dev/nfs rw " \ + "nfsroot=192.168.0.1:/export/rfs ip=192.168.0.20" + +#define CONFIG_BOOTCOMMAND \ + "tftp 0x48080000 Image; " \ + "tftp 0x48000000 Image-r8a7797-eagle.dtb; " \ + "booti 0x48080000 - 0x48000000" + +#endif /* __EAGLE_H */ -- 1.9.1