From ff0bbc92aeb87872b0c8e7e05a1604bd8c1c3e98 Mon Sep 17 00:00:00 2001 From: Vladimir Barinov Date: Mon, 22 Jan 2018 13:57:14 +0300 Subject: [PATCH] arm: renesas: Add Renesas R8A7798 SoC support This adds Renesas R8A7798 SoC support Signed-off-by: Vladimir Barinov Signed-off-by: Mikhail Ulyanov --- arch/arm/cpu/armv8/Kconfig | 3 + arch/arm/cpu/armv8/rcar_gen3/Makefile | 3 + arch/arm/cpu/armv8/rcar_gen3/cpu_info-r8a7798.c | 40 + arch/arm/cpu/armv8/rcar_gen3/cpu_info.c | 8 + arch/arm/cpu/armv8/rcar_gen3/pfc-r8a7798.c | 3074 ++++++++++++++++++++ arch/arm/cpu/armv8/rcar_gen3/pfc.c | 2 + arch/arm/include/asm/arch-rcar_gen3/gpio.h | 4 + arch/arm/include/asm/arch-rcar_gen3/r8a7798-gpio.h | 522 ++++ arch/arm/include/asm/arch-rcar_gen3/r8a7798.h | 34 + arch/arm/include/asm/arch-rcar_gen3/rcar_gen3.h | 2 + drivers/mtd/spi/sf_probe.c | 2 +- drivers/net/Kconfig | 2 +- drivers/net/sh_eth.c | 11 +- drivers/net/sh_eth.h | 7 +- drivers/serial/serial_sh.h | 2 +- include/configs/rcar-gen3-common.h | 6 + 16 files changed, 3715 insertions(+), 7 deletions(-) create mode 100644 arch/arm/cpu/armv8/rcar_gen3/cpu_info-r8a7798.c create mode 100644 arch/arm/cpu/armv8/rcar_gen3/pfc-r8a7798.c create mode 100644 arch/arm/include/asm/arch-rcar_gen3/r8a7798-gpio.h create mode 100644 arch/arm/include/asm/arch-rcar_gen3/r8a7798.h diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig index 343b121..58a9259 100644 --- a/arch/arm/cpu/armv8/Kconfig +++ b/arch/arm/cpu/armv8/Kconfig @@ -44,6 +44,9 @@ config R8A77965 config R8A7797 bool "Renesas SoC R8A7797" +config R8A7798 + bool "Renesas SoC R8A7798" + endchoice config SYS_SOC diff --git a/arch/arm/cpu/armv8/rcar_gen3/Makefile b/arch/arm/cpu/armv8/rcar_gen3/Makefile index a7a8f79..a8b7ddf 100644 --- a/arch/arm/cpu/armv8/rcar_gen3/Makefile +++ b/arch/arm/cpu/armv8/rcar_gen3/Makefile @@ -18,3 +18,6 @@ obj-$(CONFIG_R8A7796X) += lowlevel_init.o cpu_info-r8a7796.o \ obj-$(CONFIG_R8A7797) += lowlevel_init.o cpu_info-r8a7797.o \ pfc.o pfc-r8a7797.o prr_depend.o \ board.o +obj-$(CONFIG_R8A7798) += lowlevel_init.o cpu_info-r8a7798.o \ + pfc.o pfc-r8a7798.o prr_depend.o \ + board.o diff --git a/arch/arm/cpu/armv8/rcar_gen3/cpu_info-r8a7798.c b/arch/arm/cpu/armv8/rcar_gen3/cpu_info-r8a7798.c new file mode 100644 index 0000000..df94cd6 --- /dev/null +++ b/arch/arm/cpu/armv8/rcar_gen3/cpu_info-r8a7798.c @@ -0,0 +1,40 @@ +/* + * arch/arm/cpu/armv8/rcar_gen3/cpu_info-r8a7798.c + * This file defines cpu information funstions. + * + * Copyright (C) 2018 Renesas Electronics Corp. + * Copyright (C) 2018 Cogent Embedded, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include +#include + +#define PRR 0xFFF00044 + +u32 rcar_get_cpu_type(void) +{ + u32 product; + + product = readl(PRR); + + return (product & 0x00007F00) >> 8; +} + +u32 rcar_get_cpu_rev_integer(void) +{ + u32 product; + + product = readl(PRR); + + return (u32)(((product & 0x000000F0) >> 4) + 1); +} + +u32 rcar_get_cpu_rev_fraction(void) +{ + u32 product; + + product = readl(PRR); + + return (u32)(product & 0x0000000F); +} diff --git a/arch/arm/cpu/armv8/rcar_gen3/cpu_info.c b/arch/arm/cpu/armv8/rcar_gen3/cpu_info.c index 0046c75..a9366c0 100644 --- a/arch/arm/cpu/armv8/rcar_gen3/cpu_info.c +++ b/arch/arm/cpu/armv8/rcar_gen3/cpu_info.c @@ -89,6 +89,14 @@ int print_cpuinfo(void) CONFIG_RCAR_TARGET_STRING); } break; + case 0x56: + printf("CPU: Renesas Electronics R8A7798 rev %d.%d\n", + rev_integer, rev_fraction); + if (strcmp(CONFIG_RCAR_TARGET_STRING, "r8a7798")) { + printf("Warning: this code supports only %s\n", + CONFIG_RCAR_TARGET_STRING); + } + break; } return 0; } diff --git a/arch/arm/cpu/armv8/rcar_gen3/pfc-r8a7798.c b/arch/arm/cpu/armv8/rcar_gen3/pfc-r8a7798.c new file mode 100644 index 0000000..40444ba --- /dev/null +++ b/arch/arm/cpu/armv8/rcar_gen3/pfc-r8a7798.c @@ -0,0 +1,3074 @@ +/* + * arch/arm/cpu/armv8/rcar_gen3/pfc-r8a7798.c + * This file is r8a7798 processor support - PFC hardware block. + * + * Copyright (C) 2018 Renesas Electronics Corp. + * Copyright (C) 2018 Cogent Embedded, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +#define CPU_32_PORT(fn, pfx, sfx) \ + PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ + PORT_10(fn, pfx##2, sfx), PORT_1(fn, pfx##30, sfx), \ + PORT_1(fn, pfx##31, sfx) + +#define CPU_32_PORT1(fn, pfx, sfx) \ + PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ + PORT_10(fn, pfx##2, sfx) + +#define CPU_32_PORT2(fn, pfx, sfx) \ + PORT_10(fn, pfx, sfx), PORT_10(fn, pfx##1, sfx), \ + PORT_10(fn, pfx##2, sfx) + +#define CPU_32_PORT_30(fn, pfx, sfx) \ + PORT_10(fn, pfx, sfx), \ + PORT_10(fn, pfx##1, sfx), \ + PORT_10(fn, pfx##2, sfx) + +#define CPU_32_PORT_28(fn, pfx, sfx) \ + PORT_10(fn, pfx, sfx), \ + PORT_10(fn, pfx##1, sfx), \ + PORT_1(fn, pfx##20, sfx), \ + PORT_1(fn, pfx##21, sfx), \ + PORT_1(fn, pfx##22, sfx), \ + PORT_1(fn, pfx##23, sfx), \ + PORT_1(fn, pfx##24, sfx), \ + PORT_1(fn, pfx##25, sfx), \ + PORT_1(fn, pfx##26, sfx), \ + PORT_1(fn, pfx##27, sfx) + +#define CPU_32_PORT_25(fn, pfx, sfx) \ + PORT_10(fn, pfx, sfx), \ + PORT_10(fn, pfx##1, sfx), \ + PORT_1(fn, pfx##20, sfx), \ + PORT_1(fn, pfx##21, sfx), \ + PORT_1(fn, pfx##22, sfx), \ + PORT_1(fn, pfx##23, sfx), \ + PORT_1(fn, pfx##24, sfx) + +#define CPU_32_PORT_22(fn, pfx, sfx) \ + PORT_10(fn, pfx, sfx), \ + PORT_10(fn, pfx##1, sfx), \ + PORT_1(fn, pfx##20, sfx), \ + PORT_1(fn, pfx##21, sfx) + +#define CPU_32_PORT_17(fn, pfx, sfx) \ + PORT_10(fn, pfx, sfx), \ + PORT_1(fn, pfx##10, sfx), \ + PORT_1(fn, pfx##11, sfx), \ + PORT_1(fn, pfx##12, sfx), \ + PORT_1(fn, pfx##13, sfx), \ + PORT_1(fn, pfx##14, sfx), \ + PORT_1(fn, pfx##15, sfx), \ + PORT_1(fn, pfx##16, sfx) + +#define CPU_32_PORT_15(fn, pfx, sfx) \ + PORT_10(fn, pfx, sfx), \ + PORT_1(fn, pfx##10, sfx), \ + PORT_1(fn, pfx##11, sfx), \ + PORT_1(fn, pfx##12, sfx), \ + PORT_1(fn, pfx##13, sfx), \ + PORT_1(fn, pfx##14, sfx) + +#define CPU_ALL_PORT(fn, pfx, sfx) \ + CPU_32_PORT_22(fn, pfx##_0_, sfx), \ + CPU_32_PORT_28(fn, pfx##_1_, sfx), \ + CPU_32_PORT_30(fn, pfx##_2_, sfx), \ + CPU_32_PORT_17(fn, pfx##_3_, sfx), \ + CPU_32_PORT_25(fn, pfx##_4_, sfx), \ + CPU_32_PORT_15(fn, pfx##_5_, sfx) + +#define _GP_GPIO(pfx, sfx) PINMUX_GPIO(GPIO_GP##pfx, GP##pfx##_DATA) +#define _GP_DATA(pfx, sfx) PINMUX_DATA(GP##pfx##_DATA, GP##pfx##_FN, \ + GP##pfx##_IN, GP##pfx##_OUT) + +#define _GP_INOUTSEL(pfx, sfx) GP##pfx##_IN, GP##pfx##_OUT +#define _GP_INDT(pfx, sfx) GP##pfx##_DATA + +#define GP_ALL(str) CPU_ALL_PORT(_PORT_ALL, GP, str) +#define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, , unused) +#define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, , unused) + + +#define PORT_10_REV(fn, pfx, sfx) \ + PORT_1(fn, pfx##9, sfx), PORT_1(fn, pfx##8, sfx), \ + PORT_1(fn, pfx##7, sfx), PORT_1(fn, pfx##6, sfx), \ + PORT_1(fn, pfx##5, sfx), PORT_1(fn, pfx##4, sfx), \ + PORT_1(fn, pfx##3, sfx), PORT_1(fn, pfx##2, sfx), \ + PORT_1(fn, pfx##1, sfx), PORT_1(fn, pfx##0, sfx) + +#define CPU_32_PORT_REV(fn, pfx, sfx) \ + PORT_1(fn, pfx##31, sfx), PORT_1(fn, pfx##30, sfx), \ + PORT_10_REV(fn, pfx##2, sfx), PORT_10_REV(fn, pfx##1, sfx), \ + PORT_10_REV(fn, pfx, sfx) + +#define GP_INOUTSEL(bank) CPU_32_PORT_REV(_GP_INOUTSEL, _##bank##_, unused) +#define GP_INDT(bank) CPU_32_PORT_REV(_GP_INDT, _##bank##_, unused) + +#define PINMUX_IPSR_IDATA(fn) PINMUX_DATA(fn##_IMARK, GFN_##fn, IFN_##fn) +#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, GFN_##ipsr, FN_##fn) +#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \ + FN_##ipsr, FN_##fn) + +enum { + PINMUX_RESERVED = 0, + + PINMUX_DATA_BEGIN, + GP_ALL(DATA), + PINMUX_DATA_END, + + PINMUX_INPUT_BEGIN, + GP_ALL(IN), + PINMUX_INPUT_END, + + PINMUX_OUTPUT_BEGIN, + GP_ALL(OUT), + PINMUX_OUTPUT_END, + + PINMUX_FUNCTION_BEGIN, + GP_ALL(FN), + + /* GPSR0 */ + GFN_DU_EXODDF_DU_ODDF_DISP_CDE, + GFN_DU_EXVSYNC_DU_VSYNC, + GFN_DU_EXHSYNC_DU_HSYNC, + GFN_DU_DOTCLKOUT, + GFN_DU_DB7, + GFN_DU_DB6, + GFN_DU_DB5, + GFN_DU_DB4, + GFN_DU_DB3, + GFN_DU_DB2, + GFN_DU_DG7, + GFN_DU_DG6, + GFN_DU_DG5, + GFN_DU_DG4, + GFN_DU_DG3, + GFN_DU_DG2, + GFN_DU_DR7, + GFN_DU_DR6, + GFN_DU_DR5, + GFN_DU_DR4, + GFN_DU_DR3, + GFN_DU_DR2, + + /* GPSR1 */ + GFN_DIGRF_CLKOUT, + GFN_DIGRF_CLKIN, + GFN_CANFD_CLK_A, + GFN_CANFD1_RX, + GFN_CANFD1_TX, + GFN_CANFD0_RX_A, + GFN_CANFD0_TX_A, + GFN_AVB0_AVTP_CAPTURE, + GFN_AVB0_AVTP_MATCH, + FN_AVB0_LINK, + FN_AVB0_PHY_INT, + FN_AVB0_MAGIC, + FN_AVB0_MDC, + FN_AVB0_MDIO, + FN_AVB0_TXCREFCLK, + FN_AVB0_TD3, + FN_AVB0_TD2, + FN_AVB0_TD1, + FN_AVB0_TD0, + FN_AVB0_TXC, + FN_AVB0_TX_CTL, + FN_AVB0_RD3, + FN_AVB0_RD2, + FN_AVB0_RD1, + FN_AVB0_RD0, + FN_AVB0_RXC, + FN_AVB0_RX_CTL, + GFN_IRQ0, + + /* GPSR2 */ + GFN_FSO_TOE_N, + GFN_FSO_CFE_1_N, + GFN_FSO_CFE_0_N, + GFN_SDA3, + GFN_SCL3, + GFN_MSIOF0_SS2, + GFN_MSIOF0_SS1, + GFN_MSIOF0_SYNC, + GFN_MSIOF0_SCK, + GFN_MSIOF0_TXD, + GFN_MSIOF0_RXD, + GFN_IRQ5, + GFN_IRQ4, + GFN_VI0_FIELD, + GFN_VI0_DATA11, + GFN_VI0_DATA10, + GFN_VI0_DATA9, + GFN_VI0_DATA8, + GFN_VI0_DATA7, + GFN_VI0_DATA6, + GFN_VI0_DATA5, + GFN_VI0_DATA4, + GFN_VI0_DATA3, + GFN_VI0_DATA2, + GFN_VI0_DATA1, + GFN_VI0_DATA0, + GFN_VI0_VSYNC_N, + GFN_VI0_HSYNC_N, + GFN_VI0_CLKENB, + GFN_VI0_CLK, + + /* GPSR3 */ + GFN_VI1_FIELD, + GFN_VI1_DATA11, + GFN_VI1_DATA10, + GFN_VI1_DATA9, + GFN_VI1_DATA8, + GFN_VI1_DATA7, + GFN_VI1_DATA6, + GFN_VI1_DATA5, + GFN_VI1_DATA4, + GFN_VI1_DATA3, + GFN_VI1_DATA2, + GFN_VI1_DATA1, + GFN_VI1_DATA0, + GFN_VI1_VSYNC_N, + GFN_VI1_HSYNC_N, + GFN_VI1_CLKENB, + GFN_VI1_CLK, + + /* GPSR4 */ + FN_GETHER_LINK_A, + FN_GETHER_PHY_INT_A, + FN_GETHER_MAGIC, + FN_GETHER_MDC_A, + FN_GETHER_MDIO_A, + FN_GETHER_TXCREFCLK_MEGA, + FN_GETHER_TXCREFCLK, + FN_GETHER_TD3, + FN_GETHER_TD2, + FN_GETHER_TD1, + FN_GETHER_TD0, + FN_GETHER_TXC, + FN_GETHER_TX_CTL, + FN_GETHER_RD3, + FN_GETHER_RD2, + FN_GETHER_RD1, + FN_GETHER_RD0, + FN_GETHER_RXC, + FN_GETHER_RX_CTL, + GFN_SDA2, + GFN_SCL2, + GFN_SDA1, + GFN_SCL1, + GFN_SDA0, + GFN_SCL0, + + /* GPSR5 */ + FN_RPC_INT_N, + FN_RPC_WP_N, + FN_RPC_RESET_N, + FN_QSPI1_SSL, + FN_QSPI1_IO3, + FN_QSPI1_IO2, + FN_QSPI1_MISO_IO1, + FN_QSPI1_MOSI_IO0, + FN_QSPI1_SPCLK, + FN_QSPI0_SSL, + FN_QSPI0_IO3, + FN_QSPI0_IO2, + FN_QSPI0_MISO_IO1, + FN_QSPI0_MOSI_IO0, + FN_QSPI0_SPCLK, + + /* IPSR0 */ + IFN_DU_DR2, + FN_SCK4, + FN_GETHER_RMII_CRS_DV, + FN_A0, + IFN_DU_DR3, + FN_RX4, + FN_GETHER_RMII_RX_ER, + FN_A1, + IFN_DU_DR4, + FN_TX4, + FN_GETHER_RMII_RXD0, + FN_A2, + IFN_DU_DR5, + FN_CTS4_N, + FN_GETHER_RMII_RXD1, + FN_A3, + IFN_DU_DR6, + FN_RTS4_N_TANS, + FN_GETHER_RMII_TXD_EN, + FN_A4, + IFN_DU_DR7, + FN_GETHER_RMII_TXD0, + FN_A5, + IFN_DU_DG2, + FN_GETHER_RMII_TXD1, + FN_A6, + IFN_DU_DG3, + FN_CPG_CPCKOUT, + FN_GETHER_RMII_REFCLK, + FN_A7, + FN_PWMFSW0, + + /* IPSR1 */ + IFN_DU_DG4, + FN_SCL5, + FN_A8, + IFN_DU_DG5, + FN_SDA5, + FN_GETHER_MDC_B, + FN_A9, + IFN_DU_DG6, + FN_SCIF_CLK_A, + FN_GETHER_MDIO_B, + FN_A10, + IFN_DU_DG7, + FN_HRX0_A, + FN_A11, + IFN_DU_DB2, + FN_HSCK0_A, + FN_A12, + FN_IRQ1, + IFN_DU_DB3, + FN_HRTS0_N_A, + FN_A13, + FN_IRQ2, + IFN_DU_DB4, + FN_HCTS0_N_A, + FN_A14, + FN_IRQ3, + IFN_DU_DB5, + FN_HTX0_A, + FN_PWM0_A, + FN_A15, + + /* IPSR2 */ + IFN_DU_DB6, + FN_MSIOF3_RXD, + FN_A16, + IFN_DU_DB7, + FN_MSIOF3_TXD, + FN_A17, + IFN_DU_DOTCLKOUT, + FN_MSIOF3_SS1, + FN_GETHER_LINK_B, + FN_A18, + IFN_DU_EXHSYNC_DU_HSYNC, + FN_MSIOF3_SS2, + FN_GETHER_PHY_INT_B, + FN_A19, + FN_FXR_TXENA_N, + IFN_DU_EXVSYNC_DU_VSYNC, + FN_MSIOF3_SCK, + FN_FXR_TXENB_N, + IFN_DU_EXODDF_DU_ODDF_DISP_CDE, + FN_MSIOF3_SYNC, + IFN_IRQ0, + FN_CC5_OSCOUT, + IFN_VI0_CLK, + FN_MSIOF2_SCK, + FN_SCK3, + FN_HSCK3, + + /* IPSR3 */ + IFN_VI0_CLKENB, + FN_MSIOF2_RXD, + FN_RX3, + FN_RD_WR_N, + FN_HCTS3_N, + IFN_VI0_HSYNC_N, + FN_MSIOF2_TXD, + FN_TX3, + FN_HRTS3_N, + IFN_VI0_VSYNC_N, + FN_MSIOF2_SYNC, + FN_CTS3_N, + FN_HTX3, + IFN_VI0_DATA0, + FN_MSIOF2_SS1, + FN_RTS3_N_TANS, + FN_HRX3, + IFN_VI0_DATA1, + FN_MSIOF2_SS2, + FN_SCK1, + FN_SPEEDIN_A, + IFN_VI0_DATA2, + FN_AVB0_AVTP_PPS, + IFN_VI0_DATA3, + FN_HSCK1, + IFN_VI0_DATA4, + FN_HRTS1_N, + FN_RX1_A, + + /* IPSR4 */ + IFN_VI0_DATA5, + FN_HCTS1_N, + FN_TX1_A, + IFN_VI0_DATA6, + FN_HTX1, + FN_CTS1_N, + IFN_VI0_DATA7, + FN_HRX1, + FN_RTS1_N_TANS, + IFN_VI0_DATA8, + FN_HSCK2, + IFN_VI0_DATA9, + FN_HCTS2_N, + FN_PWM1_A, + FN_FSO_CFE_0_N_B, + IFN_VI0_DATA10, + FN_HRTS2_N, + FN_PWM2_A, + IFN_VI0_DATA11, + FN_HTX2, + FN_PWM3_A, + IFN_VI0_FIELD, + FN_HRX2, + FN_PWM4_A, + FN_CS1_N, + FN_FSCLKST2_N_A, + + /* IPSR5 */ + IFN_VI1_CLK, + FN_MSIOF1_RXD, + FN_CS0_N, + IFN_VI1_CLKENB, + FN_MSIOF1_TXD, + FN_D0, + IFN_VI1_HSYNC_N, + FN_MSIOF1_SCK, + FN_D1, + IFN_VI1_VSYNC_N, + FN_MSIOF1_SYNC, + FN_D2, + IFN_VI1_DATA0, + FN_MSIOF1_SS1, + FN_D3, + FN_MMC_WP, + IFN_VI1_DATA1, + FN_MSIOF1_SS2, + FN_D4, + FN_MMC_CD, + IFN_VI1_DATA2, + FN_CANFD0_TX_B, + FN_D5, + FN_MMC_DS, + IFN_VI1_DATA3, + FN_CANFD0_RX_B, + FN_D6, + FN_MMC_CMD, + + /* IPSR6 */ + IFN_VI1_DATA4, + FN_CANFD_CLK_B, + FN_D7, + FN_MMC_D0, + IFN_VI1_DATA5, + FN_D8, + FN_MMC_D1, + IFN_VI1_DATA6, + FN_D9, + FN_MMC_D2, + IFN_VI1_DATA7, + FN_D10, + FN_MMC_D3, + IFN_VI1_DATA8, + FN_D11, + FN_MMC_CLK, + IFN_VI1_DATA9, + FN_TCLK1_A, + FN_D12, + FN_MMC_D4, + IFN_VI1_DATA10, + FN_TCLK2_A, + FN_D13, + FN_MMC_D5, + IFN_VI1_DATA11, + FN_SCL4, + FN_D14, + FN_MMC_D6, + + /* IPSR7 */ + IFN_VI1_FIELD, + FN_SDA4, + FN_D15, + FN_MMC_D7, + IFN_SCL0, + FN_CLKOUT, + IFN_SDA0, + FN_BS_N, + FN_SCK0, + FN_HSCK0_B, + IFN_SCL1, + FN_TPU0TO2, + FN_RD_N, + FN_CTS0_N, + FN_HCTS0_N_B, + IFN_SDA1, + FN_TPU0TO3, + FN_WE0_N, + FN_RTS0_N_TANS, + FN_HRTS0_N_B, + IFN_SCL2, + FN_WE1_N, + FN_RX0, + FN_HRX0_B, + IFN_SDA2, + FN_EX_WAIT0, + FN_TX0, + FN_HTX0_B, + IFN_AVB0_AVTP_MATCH, + FN_TPU0TO0, + + /* IPSR8 */ + IFN_AVB0_AVTP_CAPTURE, + FN_TPU0TO1, + IFN_CANFD0_TX_A, + FN_FXR_TXDA, + FN_PWM0_B, + FN_DU_DISP, + IFN_CANFD0_RX_A, + FN_RXDA_EXTFXR, + FN_PWM1_B, + FN_DU_CDE, + IFN_CANFD1_TX, + FN_FXR_TXDB, + FN_PWM2_B, + FN_TCLK1_B, + FN_TX1_B, + IFN_CANFD1_RX, + FN_RXDB_EXTFXR, + FN_PWM3_B, + FN_TCLK2_B, + FN_RX1_B, + IFN_CANFD_CLK_A, + FN_CLK_EXTFXR, + FN_PWM4_B, + FN_SPEEDIN_B, + FN_SCIF_CLK_B, + IFN_DIGRF_CLKIN, + FN_DIGRF_CLKEN_IN, + IFN_DIGRF_CLKOUT, + FN_DIGRF_CLKEN_OUT, + + /* IPSR9 */ + IFN_IRQ4, + FN_VI0_DATA12, + IFN_IRQ5, + FN_VI0_DATA13, + IFN_MSIOF0_RXD, + FN_DU_DR0, + FN_VI0_DATA14, + IFN_MSIOF0_TXD, + FN_DU_DR1, + FN_VI0_DATA15, + IFN_MSIOF0_SCK, + FN_DU_DG0, + FN_VI0_DATA16, + IFN_MSIOF0_SYNC, + FN_DU_DG1, + FN_VI0_DATA17, + IFN_MSIOF0_SS1, + FN_DU_DB0, + FN_TCLK3, + FN_VI0_DATA18, + IFN_MSIOF0_SS2, + FN_DU_DB1, + FN_TCLK4, + FN_VI0_DATA19, + + /* IPSR10 */ + IFN_SCL3, + FN_VI0_DATA20, + IFN_SDA3, + FN_VI0_DATA21, + IFN_FSO_CFE_0_N, + FN_VI0_DATA22, + IFN_FSO_CFE_1_N, + FN_VI0_DATA23, + IFN_FSO_TOE_N, + + /* MOD_SEL0 */ + FN_SEL_CANFD0_0, FN_SEL_CANFD0_1, + FN_SEL_GETHER_0, FN_SEL_GETHER_1, + FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, + FN_SEL_PWM0_0, FN_SEL_PWM0_1, + FN_SEL_PWM1_0, FN_SEL_PWM1_1, + FN_SEL_PWM2_0, FN_SEL_PWM2_1, + FN_SEL_PWM3_0, FN_SEL_PWM3_1, + FN_SEL_PWM4_0, FN_SEL_PWM4_1, + FN_SEL_RSP_0, FN_SEL_RSP_1, + FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, + FN_SEL_TMU_0, FN_SEL_TMU_1, + + PINMUX_FUNCTION_END, + + PINMUX_MARK_BEGIN, + + /* GPSR0 */ + DU_EXODDF_DU_ODDF_DISP_CDE_GMARK, + DU_EXVSYNC_DU_VSYNC_GMARK, + DU_EXHSYNC_DU_HSYNC_GMARK, + DU_DOTCLKOUT_GMARK, + DU_DB7_GMARK, + DU_DB6_GMARK, + DU_DB5_GMARK, + DU_DB4_GMARK, + DU_DB3_GMARK, + DU_DB2_GMARK, + DU_DG7_GMARK, + DU_DG6_GMARK, + DU_DG5_GMARK, + DU_DG4_GMARK, + DU_DG3_GMARK, + DU_DG2_GMARK, + DU_DR7_GMARK, + DU_DR6_GMARK, + DU_DR5_GMARK, + DU_DR4_GMARK, + DU_DR3_GMARK, + DU_DR2_GMARK, + + /* GPSR1 */ + DIGRF_CLKOUT_GMARK, + DIGRF_CLKIN_GMARK, + CANFD_CLK_A_GMARK, + CANFD1_RX_GMARK, + CANFD1_TX_GMARK, + CANFD0_RX_A_GMARK, + CANFD0_TX_A_GMARK, + AVB0_AVTP_CAPTURE_GMARK, + AVB0_AVTP_MATCH_GMARK, + AVB0_LINK_MARK, + AVB0_PHY_INT_MARK, + AVB0_MAGIC_MARK, + AVB0_MDC_MARK, + AVB0_MDIO_MARK, + AVB0_TXCREFCLK_MARK, + AVB0_TD3_MARK, + AVB0_TD2_MARK, + AVB0_TD1_MARK, + AVB0_TD0_MARK, + AVB0_TXC_MARK, + AVB0_TX_CTL_MARK, + AVB0_RD3_MARK, + AVB0_RD2_MARK, + AVB0_RD1_MARK, + AVB0_RD0_MARK, + AVB0_RXC_MARK, + AVB0_RX_CTL_MARK, + IRQ0_GMARK, + + /* GPSR2 */ + FSO_TOE_N_GMARK, + FSO_CFE_1_N_GMARK, + FSO_CFE_0_N_GMARK, + SDA3_GMARK, + SCL3_GMARK, + MSIOF0_SS2_GMARK, + MSIOF0_SS1_GMARK, + MSIOF0_SYNC_GMARK, + MSIOF0_SCK_GMARK, + MSIOF0_TXD_GMARK, + MSIOF0_RXD_GMARK, + IRQ5_GMARK, + IRQ4_GMARK, + VI0_FIELD_GMARK, + VI0_DATA11_GMARK, + VI0_DATA10_GMARK, + VI0_DATA9_GMARK, + VI0_DATA8_GMARK, + VI0_DATA7_GMARK, + VI0_DATA6_GMARK, + VI0_DATA5_GMARK, + VI0_DATA4_GMARK, + VI0_DATA3_GMARK, + VI0_DATA2_GMARK, + VI0_DATA1_GMARK, + VI0_DATA0_GMARK, + VI0_VSYNC_N_GMARK, + VI0_HSYNC_N_GMARK, + VI0_CLKENB_GMARK, + VI0_CLK_GMARK, + + /* GPSR3 */ + VI1_FIELD_GMARK, + VI1_DATA11_GMARK, + VI1_DATA10_GMARK, + VI1_DATA9_GMARK, + VI1_DATA8_GMARK, + VI1_DATA7_GMARK, + VI1_DATA6_GMARK, + VI1_DATA5_GMARK, + VI1_DATA4_GMARK, + VI1_DATA3_GMARK, + VI1_DATA2_GMARK, + VI1_DATA1_GMARK, + VI1_DATA0_GMARK, + VI1_VSYNC_N_GMARK, + VI1_HSYNC_N_GMARK, + VI1_CLKENB_GMARK, + VI1_CLK_GMARK, + + /* GPSR4 */ + GETHER_LINK_A_MARK, + GETHER_PHY_INT_A_MARK, + GETHER_MAGIC_MARK, + GETHER_MDC_A_MARK, + GETHER_MDIO_A_MARK, + GETHER_TXCREFCLK_MEGA_MARK, + GETHER_TXCREFCLK_MARK, + GETHER_TD3_MARK, + GETHER_TD2_MARK, + GETHER_TD1_MARK, + GETHER_TD0_MARK, + GETHER_TXC_MARK, + GETHER_TX_CTL_MARK, + GETHER_RD3_MARK, + GETHER_RD2_MARK, + GETHER_RD1_MARK, + GETHER_RD0_MARK, + GETHER_RXC_MARK, + GETHER_RX_CTL_MARK, + SDA2_GMARK, + SCL2_GMARK, + SDA1_GMARK, + SCL1_GMARK, + SDA0_GMARK, + SCL0_GMARK, + + /* GPSR5 */ + RPC_INT_N_MARK, + RPC_WP_N_MARK, + RPC_RESET_N_MARK, + QSPI1_SSL_MARK, + QSPI1_IO3_MARK, + QSPI1_IO2_MARK, + QSPI1_MISO_IO1_MARK, + QSPI1_MOSI_IO0_MARK, + QSPI1_SPCLK_MARK, + QSPI0_SSL_MARK, + QSPI0_IO3_MARK, + QSPI0_IO2_MARK, + QSPI0_MISO_IO1_MARK, + QSPI0_MOSI_IO0_MARK, + QSPI0_SPCLK_MARK, + + /* IPSR0 */ + DU_DR2_IMARK, + SCK4_MARK, + GETHER_RMII_CRS_DV_MARK, + A0_MARK, + DU_DR3_IMARK, + RX4_MARK, + GETHER_RMII_RX_ER_MARK, + A1_MARK, + DU_DR4_IMARK, + TX4_MARK, + GETHER_RMII_RXD0_MARK, + A2_MARK, + DU_DR5_IMARK, + CTS4_N_MARK, + GETHER_RMII_RXD1_MARK, + A3_MARK, + DU_DR6_IMARK, + RTS4_N_TANS_MARK, + GETHER_RMII_TXD_EN_MARK, + A4_MARK, + DU_DR7_IMARK, + GETHER_RMII_TXD0_MARK, + A5_MARK, + DU_DG2_IMARK, + GETHER_RMII_TXD1_MARK, + A6_MARK, + DU_DG3_IMARK, + CPG_CPCKOUT_MARK, + GETHER_RMII_REFCLK_MARK, + A7_MARK, + PWMFSW0_MARK, + + /* IPSR1 */ + DU_DG4_IMARK, + SCL5_MARK, + A8_MARK, + DU_DG5_IMARK, + SDA5_MARK, + GETHER_MDC_B_MARK, + A9_MARK, + DU_DG6_IMARK, + SCIF_CLK_A_MARK, + GETHER_MDIO_B_MARK, + A10_MARK, + DU_DG7_IMARK, + HRX0_A_MARK, + A11_MARK, + DU_DB2_IMARK, + HSCK0_A_MARK, + A12_MARK, + IRQ1_MARK, + DU_DB3_IMARK, + HRTS0_N_A_MARK, + A13_MARK, + IRQ2_MARK, + DU_DB4_IMARK, + HCTS0_N_A_MARK, + A14_MARK, + IRQ3_MARK, + DU_DB5_IMARK, + HTX0_A_MARK, + PWM0_A_MARK, + A15_MARK, + + /* IPSR2 */ + DU_DB6_IMARK, + MSIOF3_RXD_MARK, + A16_MARK, + DU_DB7_IMARK, + MSIOF3_TXD_MARK, + A17_MARK, + DU_DOTCLKOUT_IMARK, + MSIOF3_SS1_MARK, + GETHER_LINK_B_MARK, + A18_MARK, + DU_EXHSYNC_DU_HSYNC_IMARK, + MSIOF3_SS2_MARK, + GETHER_PHY_INT_B_MARK, + A19_MARK, + FXR_TXENA_N_MARK, + DU_EXVSYNC_DU_VSYNC_IMARK, + MSIOF3_SCK_MARK, + FXR_TXENB_N_MARK, + DU_EXODDF_DU_ODDF_DISP_CDE_IMARK, + MSIOF3_SYNC_MARK, + IRQ0_IMARK, + CC5_OSCOUT_MARK, + VI0_CLK_IMARK, + MSIOF2_SCK_MARK, + SCK3_MARK, + HSCK3_MARK, + + /* IPSR3 */ + VI0_CLKENB_IMARK, + MSIOF2_RXD_MARK, + RX3_MARK, + RD_WR_N_MARK, + HCTS3_N_MARK, + VI0_HSYNC_N_IMARK, + MSIOF2_TXD_MARK, + TX3_MARK, + HRTS3_N_MARK, + VI0_VSYNC_N_IMARK, + MSIOF2_SYNC_MARK, + CTS3_N_MARK, + HTX3_MARK, + VI0_DATA0_IMARK, + MSIOF2_SS1_MARK, + RTS3_N_TANS_MARK, + HRX3_MARK, + VI0_DATA1_IMARK, + MSIOF2_SS2_MARK, + SCK1_MARK, + SPEEDIN_A_MARK, + VI0_DATA2_IMARK, + AVB0_AVTP_PPS_MARK, + VI0_DATA3_IMARK, + HSCK1_MARK, + VI0_DATA4_IMARK, + HRTS1_N_MARK, + RX1_A_MARK, + + /* IPSR4 */ + VI0_DATA5_IMARK, + HCTS1_N_MARK, + TX1_A_MARK, + VI0_DATA6_IMARK, + HTX1_MARK, + CTS1_N_MARK, + VI0_DATA7_IMARK, + HRX1_MARK, + RTS1_N_TANS_MARK, + VI0_DATA8_IMARK, + HSCK2_MARK, + VI0_DATA9_IMARK, + HCTS2_N_MARK, + PWM1_A_MARK, + FSO_CFE_0_N_B_MARK, + VI0_DATA10_IMARK, + HRTS2_N_MARK, + PWM2_A_MARK, + VI0_DATA11_IMARK, + HTX2_MARK, + PWM3_A_MARK, + VI0_FIELD_IMARK, + HRX2_MARK, + PWM4_A_MARK, + CS1_N_MARK, + FSCLKST2_N_A_MARK, + + /* IPSR5 */ + VI1_CLK_IMARK, + MSIOF1_RXD_MARK, + CS0_N_MARK, + VI1_CLKENB_IMARK, + MSIOF1_TXD_MARK, + D0_MARK, + VI1_HSYNC_N_IMARK, + MSIOF1_SCK_MARK, + D1_MARK, + VI1_VSYNC_N_IMARK, + MSIOF1_SYNC_MARK, + D2_MARK, + VI1_DATA0_IMARK, + MSIOF1_SS1_MARK, + D3_MARK, + MMC_WP_MARK, + VI1_DATA1_IMARK, + MSIOF1_SS2_MARK, + D4_MARK, + MMC_CD_MARK, + VI1_DATA2_IMARK, + CANFD0_TX_B_MARK, + D5_MARK, + MMC_DS_MARK, + VI1_DATA3_IMARK, + CANFD0_RX_B_MARK, + D6_MARK, + MMC_CMD_MARK, + + /* IPSR6 */ + VI1_DATA4_IMARK, + CANFD_CLK_B_MARK, + D7_MARK, + MMC_D0_MARK, + VI1_DATA5_IMARK, + D8_MARK, + MMC_D1_MARK, + VI1_DATA6_IMARK, + D9_MARK, + MMC_D2_MARK, + VI1_DATA7_IMARK, + D10_MARK, + MMC_D3_MARK, + VI1_DATA8_IMARK, + D11_MARK, + MMC_CLK_MARK, + VI1_DATA9_IMARK, + TCLK1_A_MARK, + D12_MARK, + MMC_D4_MARK, + VI1_DATA10_IMARK, + TCLK2_A_MARK, + D13_MARK, + MMC_D5_MARK, + VI1_DATA11_IMARK, + SCL4_MARK, + D14_MARK, + MMC_D6_MARK, + + /* IPSR7 */ + VI1_FIELD_IMARK, + SDA4_MARK, + D15_MARK, + MMC_D7_MARK, + SCL0_IMARK, + CLKOUT_MARK, + SDA0_IMARK, + BS_N_MARK, + SCK0_MARK, + HSCK0_B_MARK, + SCL1_IMARK, + TPU0TO2_MARK, + RD_N_MARK, + CTS0_N_MARK, + HCTS0_N_B_MARK, + SDA1_IMARK, + TPU0TO3_MARK, + WE0_N_MARK, + RTS0_N_TANS_MARK, + HRTS0_N_B_MARK, + SCL2_IMARK, + WE1_N_MARK, + RX0_MARK, + HRX0_B_MARK, + SDA2_IMARK, + EX_WAIT0_MARK, + TX0_MARK, + HTX0_B_MARK, + AVB0_AVTP_MATCH_IMARK, + TPU0TO0_MARK, + + /* IPSR8 */ + AVB0_AVTP_CAPTURE_IMARK, + TPU0TO1_MARK, + CANFD0_TX_A_IMARK, + FXR_TXDA_MARK, + PWM0_B_MARK, + DU_DISP_MARK, + CANFD0_RX_A_IMARK, + RXDA_EXTFXR_MARK, + PWM1_B_MARK, + DU_CDE_MARK, + CANFD1_TX_IMARK, + FXR_TXDB_MARK, + PWM2_B_MARK, + TCLK1_B_MARK, + TX1_B_MARK, + CANFD1_RX_IMARK, + RXDB_EXTFXR_MARK, + PWM3_B_MARK, + TCLK2_B_MARK, + RX1_B_MARK, + CANFD_CLK_A_IMARK, + CLK_EXTFXR_MARK, + PWM4_B_MARK, + SPEEDIN_B_MARK, + SCIF_CLK_B_MARK, + DIGRF_CLKIN_IMARK, + DIGRF_CLKEN_IN_MARK, + DIGRF_CLKOUT_IMARK, + DIGRF_CLKEN_OUT_MARK, + + /* IPSR9 */ + IRQ4_IMARK, + VI0_DATA12_MARK, + IRQ5_IMARK, + VI0_DATA13_MARK, + MSIOF0_RXD_IMARK, + DU_DR0_MARK, + VI0_DATA14_MARK, + MSIOF0_TXD_IMARK, + DU_DR1_MARK, + VI0_DATA15_MARK, + MSIOF0_SCK_IMARK, + DU_DG0_MARK, + VI0_DATA16_MARK, + MSIOF0_SYNC_IMARK, + DU_DG1_MARK, + VI0_DATA17_MARK, + MSIOF0_SS1_IMARK, + DU_DB0_MARK, + TCLK3_MARK, + VI0_DATA18_MARK, + MSIOF0_SS2_IMARK, + DU_DB1_MARK, + TCLK4_MARK, + VI0_DATA19_MARK, + + /* IPSR10 */ + SCL3_IMARK, + VI0_DATA20_MARK, + SDA3_IMARK, + VI0_DATA21_MARK, + FSO_CFE_0_N_IMARK, + VI0_DATA22_MARK, + FSO_CFE_1_N_IMARK, + VI0_DATA23_MARK, + FSO_TOE_N_IMARK, + + PINMUX_MARK_END, +}; + +static pinmux_enum_t pinmux_data[] = { + PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */ + + /* GPSR0 */ + PINMUX_DATA(DU_EXODDF_DU_ODDF_DISP_CDE_GMARK, GFN_DU_EXODDF_DU_ODDF_DISP_CDE), + PINMUX_DATA(DU_EXVSYNC_DU_VSYNC_GMARK, GFN_DU_EXVSYNC_DU_VSYNC), + PINMUX_DATA(DU_EXHSYNC_DU_HSYNC_GMARK, GFN_DU_EXHSYNC_DU_HSYNC), + PINMUX_DATA(DU_DOTCLKOUT_GMARK, GFN_DU_DOTCLKOUT), + PINMUX_DATA(DU_DB7_GMARK, GFN_DU_DB7), + PINMUX_DATA(DU_DB6_GMARK, GFN_DU_DB6), + PINMUX_DATA(DU_DB5_GMARK, GFN_DU_DB5), + PINMUX_DATA(DU_DB4_GMARK, GFN_DU_DB4), + PINMUX_DATA(DU_DB3_GMARK, GFN_DU_DB3), + PINMUX_DATA(DU_DB2_GMARK, GFN_DU_DB2), + PINMUX_DATA(DU_DG7_GMARK, GFN_DU_DG7), + PINMUX_DATA(DU_DG6_GMARK, GFN_DU_DG6), + PINMUX_DATA(DU_DG5_GMARK, GFN_DU_DG5), + PINMUX_DATA(DU_DG4_GMARK, GFN_DU_DG4), + PINMUX_DATA(DU_DG3_GMARK, GFN_DU_DG3), + PINMUX_DATA(DU_DG2_GMARK, GFN_DU_DG2), + PINMUX_DATA(DU_DR7_GMARK, GFN_DU_DR7), + PINMUX_DATA(DU_DR6_GMARK, GFN_DU_DR6), + PINMUX_DATA(DU_DR5_GMARK, GFN_DU_DR5), + PINMUX_DATA(DU_DR4_GMARK, GFN_DU_DR4), + PINMUX_DATA(DU_DR3_GMARK, GFN_DU_DR3), + PINMUX_DATA(DU_DR2_GMARK, GFN_DU_DR2), + + /* GPSR1 */ + PINMUX_DATA(DIGRF_CLKOUT_GMARK, GFN_DIGRF_CLKOUT), + PINMUX_DATA(DIGRF_CLKIN_GMARK, GFN_DIGRF_CLKIN), + PINMUX_DATA(CANFD_CLK_A_GMARK, GFN_CANFD_CLK_A), + PINMUX_DATA(CANFD1_RX_GMARK, GFN_CANFD1_RX), + PINMUX_DATA(CANFD1_TX_GMARK, GFN_CANFD1_TX), + PINMUX_DATA(CANFD0_RX_A_GMARK, GFN_CANFD0_RX_A), + PINMUX_DATA(CANFD0_TX_A_GMARK, GFN_CANFD0_TX_A), + PINMUX_DATA(AVB0_AVTP_CAPTURE_GMARK, GFN_AVB0_AVTP_CAPTURE), + PINMUX_DATA(AVB0_AVTP_MATCH_GMARK, GFN_AVB0_AVTP_MATCH), + PINMUX_DATA(AVB0_LINK_MARK, FN_AVB0_LINK), + PINMUX_DATA(AVB0_PHY_INT_MARK, FN_AVB0_PHY_INT), + PINMUX_DATA(AVB0_MAGIC_MARK, FN_AVB0_MAGIC), + PINMUX_DATA(AVB0_MDC_MARK, FN_AVB0_MDC), + PINMUX_DATA(AVB0_MDIO_MARK, FN_AVB0_MDIO), + PINMUX_DATA(AVB0_TXCREFCLK_MARK, FN_AVB0_TXCREFCLK), + PINMUX_DATA(AVB0_TD3_MARK, FN_AVB0_TD3), + PINMUX_DATA(AVB0_TD2_MARK, FN_AVB0_TD2), + PINMUX_DATA(AVB0_TD1_MARK, FN_AVB0_TD1), + PINMUX_DATA(AVB0_TD0_MARK, FN_AVB0_TD0), + PINMUX_DATA(AVB0_TXC_MARK, FN_AVB0_TXC), + PINMUX_DATA(AVB0_TX_CTL_MARK, FN_AVB0_TX_CTL), + PINMUX_DATA(AVB0_RD3_MARK, FN_AVB0_RD3), + PINMUX_DATA(AVB0_RD2_MARK, FN_AVB0_RD2), + PINMUX_DATA(AVB0_RD1_MARK, FN_AVB0_RD1), + PINMUX_DATA(AVB0_RD0_MARK, FN_AVB0_RD0), + PINMUX_DATA(AVB0_RXC_MARK, FN_AVB0_RXC), + PINMUX_DATA(AVB0_RX_CTL_MARK, FN_AVB0_RX_CTL), + PINMUX_DATA(IRQ0_GMARK, GFN_IRQ0), + + /* GPSR2 */ + PINMUX_DATA(FSO_TOE_N_GMARK, GFN_FSO_TOE_N), + PINMUX_DATA(FSO_CFE_1_N_GMARK, GFN_FSO_CFE_1_N), + PINMUX_DATA(FSO_CFE_0_N_GMARK, GFN_FSO_CFE_0_N), + PINMUX_DATA(SDA3_GMARK, GFN_SDA3), + PINMUX_DATA(SCL3_GMARK, GFN_SCL3), + PINMUX_DATA(MSIOF0_SS2_GMARK, GFN_MSIOF0_SS2), + PINMUX_DATA(MSIOF0_SS1_GMARK, GFN_MSIOF0_SS1), + PINMUX_DATA(MSIOF0_SYNC_GMARK, GFN_MSIOF0_SYNC), + PINMUX_DATA(MSIOF0_SCK_GMARK, GFN_MSIOF0_SCK), + PINMUX_DATA(MSIOF0_TXD_GMARK, GFN_MSIOF0_TXD), + PINMUX_DATA(MSIOF0_RXD_GMARK, GFN_MSIOF0_RXD), + PINMUX_DATA(IRQ5_GMARK, GFN_IRQ5), + PINMUX_DATA(IRQ4_GMARK, GFN_IRQ4), + PINMUX_DATA(VI0_FIELD_GMARK, GFN_VI0_FIELD), + PINMUX_DATA(VI0_DATA11_GMARK, GFN_VI0_DATA11), + PINMUX_DATA(VI0_DATA10_GMARK, GFN_VI0_DATA10), + PINMUX_DATA(VI0_DATA9_GMARK, GFN_VI0_DATA9), + PINMUX_DATA(VI0_DATA8_GMARK, GFN_VI0_DATA8), + PINMUX_DATA(VI0_DATA7_GMARK, GFN_VI0_DATA7), + PINMUX_DATA(VI0_DATA6_GMARK, GFN_VI0_DATA6), + PINMUX_DATA(VI0_DATA5_GMARK, GFN_VI0_DATA5), + PINMUX_DATA(VI0_DATA4_GMARK, GFN_VI0_DATA4), + PINMUX_DATA(VI0_DATA3_GMARK, GFN_VI0_DATA3), + PINMUX_DATA(VI0_DATA2_GMARK, GFN_VI0_DATA2), + PINMUX_DATA(VI0_DATA1_GMARK, GFN_VI0_DATA1), + PINMUX_DATA(VI0_DATA0_GMARK, GFN_VI0_DATA0), + PINMUX_DATA(VI0_VSYNC_N_GMARK, GFN_VI0_VSYNC_N), + PINMUX_DATA(VI0_HSYNC_N_GMARK, GFN_VI0_HSYNC_N), + PINMUX_DATA(VI0_CLKENB_GMARK, GFN_VI0_CLKENB), + PINMUX_DATA(VI0_CLK_GMARK, GFN_VI0_CLK), + + /* GPSR3 */ + PINMUX_DATA(VI1_FIELD_GMARK, GFN_VI1_FIELD), + PINMUX_DATA(VI1_DATA11_GMARK, GFN_VI1_DATA11), + PINMUX_DATA(VI1_DATA10_GMARK, GFN_VI1_DATA10), + PINMUX_DATA(VI1_DATA9_GMARK, GFN_VI1_DATA9), + PINMUX_DATA(VI1_DATA8_GMARK, GFN_VI1_DATA8), + PINMUX_DATA(VI1_DATA7_GMARK, GFN_VI1_DATA7), + PINMUX_DATA(VI1_DATA6_GMARK, GFN_VI1_DATA6), + PINMUX_DATA(VI1_DATA5_GMARK, GFN_VI1_DATA5), + PINMUX_DATA(VI1_DATA4_GMARK, GFN_VI1_DATA4), + PINMUX_DATA(VI1_DATA3_GMARK, GFN_VI1_DATA3), + PINMUX_DATA(VI1_DATA2_GMARK, GFN_VI1_DATA2), + PINMUX_DATA(VI1_DATA1_GMARK, GFN_VI1_DATA1), + PINMUX_DATA(VI1_DATA0_GMARK, GFN_VI1_DATA0), + PINMUX_DATA(VI1_VSYNC_N_GMARK, GFN_VI1_VSYNC_N), + PINMUX_DATA(VI1_HSYNC_N_GMARK, GFN_VI1_HSYNC_N), + PINMUX_DATA(VI1_CLKENB_GMARK, GFN_VI1_CLKENB), + PINMUX_DATA(VI1_CLK_GMARK, GFN_VI1_CLK), + + /* GPSR4 */ + PINMUX_DATA(GETHER_LINK_A_MARK, FN_GETHER_LINK_A), + PINMUX_DATA(GETHER_PHY_INT_A_MARK, FN_GETHER_PHY_INT_A), + PINMUX_DATA(GETHER_MAGIC_MARK, FN_GETHER_MAGIC), + PINMUX_DATA(GETHER_MDC_A_MARK, FN_GETHER_MDC_A), + PINMUX_DATA(GETHER_MDIO_A_MARK, FN_GETHER_MDIO_A), + PINMUX_DATA(GETHER_TXCREFCLK_MEGA_MARK, FN_GETHER_TXCREFCLK_MEGA), + PINMUX_DATA(GETHER_TXCREFCLK_MARK, FN_GETHER_TXCREFCLK), + PINMUX_DATA(GETHER_TD3_MARK, FN_GETHER_TD3), + PINMUX_DATA(GETHER_TD2_MARK, FN_GETHER_TD2), + PINMUX_DATA(GETHER_TD1_MARK, FN_GETHER_TD1), + PINMUX_DATA(GETHER_TD0_MARK, FN_GETHER_TD0), + PINMUX_DATA(GETHER_TXC_MARK, FN_GETHER_TXC), + PINMUX_DATA(GETHER_TX_CTL_MARK, FN_GETHER_TX_CTL), + PINMUX_DATA(GETHER_RD3_MARK, FN_GETHER_RD3), + PINMUX_DATA(GETHER_RD2_MARK, FN_GETHER_RD2), + PINMUX_DATA(GETHER_RD1_MARK, FN_GETHER_RD1), + PINMUX_DATA(GETHER_RD0_MARK, FN_GETHER_RD0), + PINMUX_DATA(GETHER_RXC_MARK, FN_GETHER_RXC), + PINMUX_DATA(GETHER_RX_CTL_MARK, FN_GETHER_RX_CTL), + PINMUX_DATA(SDA2_GMARK, GFN_SDA2), + PINMUX_DATA(SCL2_GMARK, GFN_SCL2), + PINMUX_DATA(SDA1_GMARK, GFN_SDA1), + PINMUX_DATA(SCL1_GMARK, GFN_SCL1), + PINMUX_DATA(SDA0_GMARK, GFN_SDA0), + PINMUX_DATA(SCL0_GMARK, GFN_SCL0), + + /* GPSR5 */ + PINMUX_DATA(RPC_INT_N_MARK, FN_RPC_INT_N), + PINMUX_DATA(RPC_WP_N_MARK, FN_RPC_WP_N), + PINMUX_DATA(RPC_RESET_N_MARK, FN_RPC_RESET_N), + PINMUX_DATA(QSPI1_SSL_MARK, FN_QSPI1_SSL), + PINMUX_DATA(QSPI1_IO3_MARK, FN_QSPI1_IO3), + PINMUX_DATA(QSPI1_IO2_MARK, FN_QSPI1_IO2), + PINMUX_DATA(QSPI1_MISO_IO1_MARK, FN_QSPI1_MISO_IO1), + PINMUX_DATA(QSPI1_MOSI_IO0_MARK, FN_QSPI1_MOSI_IO0), + PINMUX_DATA(QSPI1_SPCLK_MARK, FN_QSPI1_SPCLK), + PINMUX_DATA(QSPI0_SSL_MARK, FN_QSPI0_SSL), + PINMUX_DATA(QSPI0_IO3_MARK, FN_QSPI0_IO3), + PINMUX_DATA(QSPI0_IO2_MARK, FN_QSPI0_IO2), + PINMUX_DATA(QSPI0_MISO_IO1_MARK, FN_QSPI0_MISO_IO1), + PINMUX_DATA(QSPI0_MOSI_IO0_MARK, FN_QSPI0_MOSI_IO0), + PINMUX_DATA(QSPI0_SPCLK_MARK, FN_QSPI0_SPCLK), + + + /* IPSR0 */ + PINMUX_IPSR_IDATA(DU_DR2), + PINMUX_IPSR_DATA(DU_DR2, SCK4), + PINMUX_IPSR_DATA(DU_DR2, GETHER_RMII_CRS_DV), + PINMUX_IPSR_DATA(DU_DR2, A0), + PINMUX_IPSR_IDATA(DU_DR3), + PINMUX_IPSR_DATA(DU_DR3, RX4), + PINMUX_IPSR_DATA(DU_DR3, GETHER_RMII_RX_ER), + PINMUX_IPSR_DATA(DU_DR3, A1), + PINMUX_IPSR_IDATA(DU_DR4), + PINMUX_IPSR_DATA(DU_DR4, TX4), + PINMUX_IPSR_DATA(DU_DR4, GETHER_RMII_RXD0), + PINMUX_IPSR_DATA(DU_DR4, A2), + PINMUX_IPSR_IDATA(DU_DR5), + PINMUX_IPSR_DATA(DU_DR5, CTS4_N), + PINMUX_IPSR_DATA(DU_DR5, GETHER_RMII_RXD1), + PINMUX_IPSR_DATA(DU_DR5, A3), + PINMUX_IPSR_IDATA(DU_DR6), + PINMUX_IPSR_DATA(DU_DR6, RTS4_N_TANS), + PINMUX_IPSR_DATA(DU_DR6, GETHER_RMII_TXD_EN), + PINMUX_IPSR_DATA(DU_DR6, A4), + PINMUX_IPSR_IDATA(DU_DR7), + PINMUX_IPSR_DATA(DU_DR7, GETHER_RMII_TXD0), + PINMUX_IPSR_DATA(DU_DR7, A5), + PINMUX_IPSR_IDATA(DU_DG2), + PINMUX_IPSR_DATA(DU_DG2, GETHER_RMII_TXD1), + PINMUX_IPSR_DATA(DU_DG2, A6), + PINMUX_IPSR_IDATA(DU_DG3), + PINMUX_IPSR_DATA(DU_DG3, CPG_CPCKOUT), + PINMUX_IPSR_DATA(DU_DG3, GETHER_RMII_REFCLK), + PINMUX_IPSR_DATA(DU_DG3, A7), + PINMUX_IPSR_DATA(DU_DG3, PWMFSW0), + + /* IPSR1 */ + PINMUX_IPSR_IDATA(DU_DG4), + PINMUX_IPSR_DATA(DU_DG4, SCL5), + PINMUX_IPSR_DATA(DU_DG4, A8), + PINMUX_IPSR_IDATA(DU_DG5), + PINMUX_IPSR_DATA(DU_DG5, SDA5), + PINMUX_IPSR_DATA(DU_DG5, GETHER_MDC_B), + PINMUX_IPSR_DATA(DU_DG5, A9), + PINMUX_IPSR_IDATA(DU_DG6), + PINMUX_IPSR_DATA(DU_DG6, SCIF_CLK_A), + PINMUX_IPSR_DATA(DU_DG6, GETHER_MDIO_B), + PINMUX_IPSR_DATA(DU_DG6, A10), + PINMUX_IPSR_IDATA(DU_DG7), + PINMUX_IPSR_DATA(DU_DG7, HRX0_A), + PINMUX_IPSR_DATA(DU_DG7, A11), + PINMUX_IPSR_IDATA(DU_DB2), + PINMUX_IPSR_DATA(DU_DB2, HSCK0_A), + PINMUX_IPSR_DATA(DU_DB2, A12), + PINMUX_IPSR_DATA(DU_DB2, IRQ1), + PINMUX_IPSR_IDATA(DU_DB3), + PINMUX_IPSR_DATA(DU_DB3, HRTS0_N_A), + PINMUX_IPSR_DATA(DU_DB3, A13), + PINMUX_IPSR_DATA(DU_DB3, IRQ2), + PINMUX_IPSR_IDATA(DU_DB4), + PINMUX_IPSR_DATA(DU_DB4, HCTS0_N_A), + PINMUX_IPSR_DATA(DU_DB4, A14), + PINMUX_IPSR_DATA(DU_DB4, IRQ3), + PINMUX_IPSR_IDATA(DU_DB5), + PINMUX_IPSR_DATA(DU_DB5, HTX0_A), + PINMUX_IPSR_DATA(DU_DB5, PWM0_A), + PINMUX_IPSR_DATA(DU_DB5, A15), + + /* IPSR2 */ + PINMUX_IPSR_IDATA(DU_DB6), + PINMUX_IPSR_DATA(DU_DB6, MSIOF3_RXD), + PINMUX_IPSR_DATA(DU_DB6, A16), + PINMUX_IPSR_IDATA(DU_DB7), + PINMUX_IPSR_DATA(DU_DB7, MSIOF3_TXD), + PINMUX_IPSR_DATA(DU_DB7, A17), + PINMUX_IPSR_IDATA(DU_DOTCLKOUT), + PINMUX_IPSR_DATA(DU_DOTCLKOUT, MSIOF3_SS1), + PINMUX_IPSR_DATA(DU_DOTCLKOUT, GETHER_LINK_B), + PINMUX_IPSR_DATA(DU_DOTCLKOUT, A18), + PINMUX_IPSR_IDATA(DU_EXHSYNC_DU_HSYNC), + PINMUX_IPSR_DATA(DU_EXHSYNC_DU_HSYNC, MSIOF3_SS2), + PINMUX_IPSR_DATA(DU_EXHSYNC_DU_HSYNC, GETHER_PHY_INT_B), + PINMUX_IPSR_DATA(DU_EXHSYNC_DU_HSYNC, A19), + PINMUX_IPSR_DATA(DU_EXHSYNC_DU_HSYNC, FXR_TXENA_N), + PINMUX_IPSR_IDATA(DU_EXVSYNC_DU_VSYNC), + PINMUX_IPSR_DATA(DU_EXVSYNC_DU_VSYNC, MSIOF3_SCK), + PINMUX_IPSR_DATA(DU_EXVSYNC_DU_VSYNC, FXR_TXENB_N), + PINMUX_IPSR_IDATA(DU_EXODDF_DU_ODDF_DISP_CDE), + PINMUX_IPSR_DATA(DU_EXODDF_DU_ODDF_DISP_CDE, MSIOF3_SYNC), + PINMUX_IPSR_IDATA(IRQ0), + PINMUX_IPSR_DATA(IRQ0, CC5_OSCOUT), + PINMUX_IPSR_IDATA(VI0_CLK), + PINMUX_IPSR_DATA(VI0_CLK, MSIOF2_SCK), + PINMUX_IPSR_DATA(VI0_CLK, SCK3), + PINMUX_IPSR_DATA(VI0_CLK, HSCK3), + + /* IPSR3 */ + PINMUX_IPSR_IDATA(VI0_CLKENB), + PINMUX_IPSR_DATA(VI0_CLKENB, MSIOF2_RXD), + PINMUX_IPSR_DATA(VI0_CLKENB, RX3), + PINMUX_IPSR_DATA(VI0_CLKENB, RD_WR_N), + PINMUX_IPSR_DATA(VI0_CLKENB, HCTS3_N), + PINMUX_IPSR_IDATA(VI0_HSYNC_N), + PINMUX_IPSR_DATA(VI0_HSYNC_N, MSIOF2_TXD), + PINMUX_IPSR_DATA(VI0_HSYNC_N, TX3), + PINMUX_IPSR_DATA(VI0_HSYNC_N, HRTS3_N), + PINMUX_IPSR_IDATA(VI0_VSYNC_N), + PINMUX_IPSR_DATA(VI0_VSYNC_N, MSIOF2_SYNC), + PINMUX_IPSR_DATA(VI0_VSYNC_N, CTS3_N), + PINMUX_IPSR_DATA(VI0_VSYNC_N, HTX3), + PINMUX_IPSR_IDATA(VI0_DATA0), + PINMUX_IPSR_DATA(VI0_DATA0, MSIOF2_SS1), + PINMUX_IPSR_DATA(VI0_DATA0, RTS3_N_TANS), + PINMUX_IPSR_DATA(VI0_DATA0, HRX3), + PINMUX_IPSR_IDATA(VI0_DATA1), + PINMUX_IPSR_DATA(VI0_DATA1, MSIOF2_SS2), + PINMUX_IPSR_DATA(VI0_DATA1, SCK1), + PINMUX_IPSR_DATA(VI0_DATA1, SPEEDIN_A), + PINMUX_IPSR_IDATA(VI0_DATA2), + PINMUX_IPSR_DATA(VI0_DATA2, AVB0_AVTP_PPS), + PINMUX_IPSR_IDATA(VI0_DATA3), + PINMUX_IPSR_DATA(VI0_DATA3, HSCK1), + PINMUX_IPSR_IDATA(VI0_DATA4), + PINMUX_IPSR_DATA(VI0_DATA4, HRTS1_N), + PINMUX_IPSR_DATA(VI0_DATA4, RX1_A), + + /* IPSR4 */ + PINMUX_IPSR_IDATA(VI0_DATA5), + PINMUX_IPSR_DATA(VI0_DATA5, HCTS1_N), + PINMUX_IPSR_DATA(VI0_DATA5, TX1_A), + PINMUX_IPSR_IDATA(VI0_DATA6), + PINMUX_IPSR_DATA(VI0_DATA6, HTX1), + PINMUX_IPSR_DATA(VI0_DATA6, CTS1_N), + PINMUX_IPSR_IDATA(VI0_DATA7), + PINMUX_IPSR_DATA(VI0_DATA7, HRX1), + PINMUX_IPSR_DATA(VI0_DATA7, RTS1_N_TANS), + PINMUX_IPSR_IDATA(VI0_DATA8), + PINMUX_IPSR_DATA(VI0_DATA8, HSCK2), + PINMUX_IPSR_IDATA(VI0_DATA9), + PINMUX_IPSR_DATA(VI0_DATA9, HCTS2_N), + PINMUX_IPSR_DATA(VI0_DATA9, PWM1_A), + PINMUX_IPSR_DATA(VI0_DATA9, FSO_CFE_0_N_B), + PINMUX_IPSR_IDATA(VI0_DATA10), + PINMUX_IPSR_DATA(VI0_DATA10, HRTS2_N), + PINMUX_IPSR_DATA(VI0_DATA10, PWM2_A), + PINMUX_IPSR_IDATA(VI0_DATA11), + PINMUX_IPSR_DATA(VI0_DATA11, HTX2), + PINMUX_IPSR_DATA(VI0_DATA11, PWM3_A), + PINMUX_IPSR_IDATA(VI0_FIELD), + PINMUX_IPSR_DATA(VI0_FIELD, HRX2), + PINMUX_IPSR_DATA(VI0_FIELD, PWM4_A), + PINMUX_IPSR_DATA(VI0_FIELD, CS1_N), + PINMUX_IPSR_DATA(VI0_FIELD, FSCLKST2_N_A), + + /* IPSR5 */ + PINMUX_IPSR_IDATA(VI1_CLK), + PINMUX_IPSR_DATA(VI1_CLK, MSIOF1_RXD), + PINMUX_IPSR_DATA(VI1_CLK, CS0_N), + PINMUX_IPSR_IDATA(VI1_CLKENB), + PINMUX_IPSR_DATA(VI1_CLKENB, MSIOF1_TXD), + PINMUX_IPSR_DATA(VI1_CLKENB, D0), + PINMUX_IPSR_IDATA(VI1_HSYNC_N), + PINMUX_IPSR_DATA(VI1_HSYNC_N, MSIOF1_SCK), + PINMUX_IPSR_DATA(VI1_HSYNC_N, D1), + PINMUX_IPSR_IDATA(VI1_VSYNC_N), + PINMUX_IPSR_DATA(VI1_VSYNC_N, MSIOF1_SYNC), + PINMUX_IPSR_DATA(VI1_VSYNC_N, D2), + PINMUX_IPSR_IDATA(VI1_DATA0), + PINMUX_IPSR_DATA(VI1_DATA0, MSIOF1_SS1), + PINMUX_IPSR_DATA(VI1_DATA0, D3), + PINMUX_IPSR_DATA(VI1_DATA0, MMC_WP), + PINMUX_IPSR_IDATA(VI1_DATA1), + PINMUX_IPSR_DATA(VI1_DATA1, MSIOF1_SS2), + PINMUX_IPSR_DATA(VI1_DATA1, D4), + PINMUX_IPSR_DATA(VI1_DATA1, MMC_CD), + PINMUX_IPSR_IDATA(VI1_DATA2), + PINMUX_IPSR_DATA(VI1_DATA2, CANFD0_TX_B), + PINMUX_IPSR_DATA(VI1_DATA2, D5), + PINMUX_IPSR_DATA(VI1_DATA2, MMC_DS), + PINMUX_IPSR_IDATA(VI1_DATA3), + PINMUX_IPSR_DATA(VI1_DATA3, CANFD0_RX_B), + PINMUX_IPSR_DATA(VI1_DATA3, D6), + PINMUX_IPSR_DATA(VI1_DATA3, MMC_CMD), + + /* IPSR6 */ + PINMUX_IPSR_IDATA(VI1_DATA4), + PINMUX_IPSR_DATA(VI1_DATA4, CANFD_CLK_B), + PINMUX_IPSR_DATA(VI1_DATA4, D7), + PINMUX_IPSR_DATA(VI1_DATA4, MMC_D0), + PINMUX_IPSR_IDATA(VI1_DATA5), + PINMUX_IPSR_DATA(VI1_DATA5, D8), + PINMUX_IPSR_DATA(VI1_DATA5, MMC_D1), + PINMUX_IPSR_IDATA(VI1_DATA6), + PINMUX_IPSR_DATA(VI1_DATA6, D9), + PINMUX_IPSR_DATA(VI1_DATA6, MMC_D2), + PINMUX_IPSR_IDATA(VI1_DATA7), + PINMUX_IPSR_DATA(VI1_DATA7, D10), + PINMUX_IPSR_DATA(VI1_DATA7, MMC_D3), + PINMUX_IPSR_IDATA(VI1_DATA8), + PINMUX_IPSR_DATA(VI1_DATA8, D11), + PINMUX_IPSR_DATA(VI1_DATA8, MMC_CLK), + PINMUX_IPSR_IDATA(VI1_DATA9), + PINMUX_IPSR_DATA(VI1_DATA9, TCLK1_A), + PINMUX_IPSR_DATA(VI1_DATA9, D12), + PINMUX_IPSR_DATA(VI1_DATA9, MMC_D4), + PINMUX_IPSR_IDATA(VI1_DATA10), + PINMUX_IPSR_DATA(VI1_DATA10, TCLK2_A), + PINMUX_IPSR_DATA(VI1_DATA10, D13), + PINMUX_IPSR_DATA(VI1_DATA10, MMC_D5), + PINMUX_IPSR_IDATA(VI1_DATA11), + PINMUX_IPSR_DATA(VI1_DATA11, SCL4), + PINMUX_IPSR_DATA(VI1_DATA11, D14), + PINMUX_IPSR_DATA(VI1_DATA11, MMC_D6), + + /* IPSR7 */ + PINMUX_IPSR_IDATA(VI1_FIELD), + PINMUX_IPSR_DATA(VI1_FIELD, SDA4), + PINMUX_IPSR_DATA(VI1_FIELD, D15), + PINMUX_IPSR_DATA(VI1_FIELD, MMC_D7), + PINMUX_IPSR_IDATA(SCL0), + PINMUX_IPSR_DATA(SCL0, CLKOUT), + PINMUX_IPSR_IDATA(SDA0), + PINMUX_IPSR_DATA(SDA0, BS_N), + PINMUX_IPSR_DATA(SDA0, SCK0), + PINMUX_IPSR_DATA(SDA0, HSCK0_B), + PINMUX_IPSR_IDATA(SCL1), + PINMUX_IPSR_DATA(SCL1, TPU0TO2), + PINMUX_IPSR_DATA(SCL1, RD_N), + PINMUX_IPSR_DATA(SCL1, CTS0_N), + PINMUX_IPSR_DATA(SCL1, HCTS0_N_B), + PINMUX_IPSR_IDATA(SDA1), + PINMUX_IPSR_DATA(SDA1, TPU0TO3), + PINMUX_IPSR_DATA(SDA1, WE0_N), + PINMUX_IPSR_DATA(SDA1, RTS0_N_TANS), + PINMUX_IPSR_DATA(SDA1, HRTS0_N_B), + PINMUX_IPSR_IDATA(SCL2), + PINMUX_IPSR_DATA(SCL2, WE1_N), + PINMUX_IPSR_DATA(SCL2, RX0), + PINMUX_IPSR_DATA(SCL2, HRX0_B), + PINMUX_IPSR_IDATA(SDA2), + PINMUX_IPSR_DATA(SDA2, EX_WAIT0), + PINMUX_IPSR_DATA(SDA2, TX0), + PINMUX_IPSR_DATA(SDA2, HTX0_B), + PINMUX_IPSR_IDATA(AVB0_AVTP_MATCH), + PINMUX_IPSR_DATA(AVB0_AVTP_MATCH, TPU0TO0), + + /* IPSR8 */ + PINMUX_IPSR_IDATA(AVB0_AVTP_CAPTURE), + PINMUX_IPSR_DATA(AVB0_AVTP_CAPTURE, TPU0TO1), + PINMUX_IPSR_IDATA(CANFD0_TX_A), + PINMUX_IPSR_DATA(CANFD0_TX_A, FXR_TXDA), + PINMUX_IPSR_DATA(CANFD0_TX_A, PWM0_B), + PINMUX_IPSR_DATA(CANFD0_TX_A, DU_DISP), + PINMUX_IPSR_IDATA(CANFD0_RX_A), + PINMUX_IPSR_DATA(CANFD0_RX_A, RXDA_EXTFXR), + PINMUX_IPSR_DATA(CANFD0_RX_A, PWM1_B), + PINMUX_IPSR_DATA(CANFD0_RX_A, DU_CDE), + PINMUX_IPSR_IDATA(CANFD1_TX), + PINMUX_IPSR_DATA(CANFD1_TX, FXR_TXDB), + PINMUX_IPSR_DATA(CANFD1_TX, PWM2_B), + PINMUX_IPSR_DATA(CANFD1_TX, TCLK1_B), + PINMUX_IPSR_DATA(CANFD1_TX, TX1_B), + PINMUX_IPSR_IDATA(CANFD1_RX), + PINMUX_IPSR_DATA(CANFD1_RX, RXDB_EXTFXR), + PINMUX_IPSR_DATA(CANFD1_RX, PWM3_B), + PINMUX_IPSR_DATA(CANFD1_RX, TCLK2_B), + PINMUX_IPSR_DATA(CANFD1_RX, RX1_B), + PINMUX_IPSR_IDATA(CANFD_CLK_A), + PINMUX_IPSR_DATA(CANFD_CLK_A, CLK_EXTFXR), + PINMUX_IPSR_DATA(CANFD_CLK_A, PWM4_B), + PINMUX_IPSR_DATA(CANFD_CLK_A, SPEEDIN_B), + PINMUX_IPSR_DATA(CANFD_CLK_A, SCIF_CLK_B), + PINMUX_IPSR_IDATA(DIGRF_CLKIN), + PINMUX_IPSR_DATA(DIGRF_CLKIN, DIGRF_CLKEN_IN), + PINMUX_IPSR_IDATA(DIGRF_CLKOUT), + PINMUX_IPSR_DATA(DIGRF_CLKOUT, DIGRF_CLKEN_OUT), + + /* IPSR9 */ + PINMUX_IPSR_IDATA(IRQ4), + PINMUX_IPSR_DATA(IRQ4, VI0_DATA12), + PINMUX_IPSR_IDATA(IRQ5), + PINMUX_IPSR_DATA(IRQ5, VI0_DATA13), + PINMUX_IPSR_IDATA(MSIOF0_RXD), + PINMUX_IPSR_DATA(MSIOF0_RXD, DU_DR0), + PINMUX_IPSR_DATA(MSIOF0_RXD, VI0_DATA14), + PINMUX_IPSR_IDATA(MSIOF0_TXD), + PINMUX_IPSR_DATA(MSIOF0_TXD, DU_DR1), + PINMUX_IPSR_DATA(MSIOF0_TXD, VI0_DATA15), + PINMUX_IPSR_IDATA(MSIOF0_SCK), + PINMUX_IPSR_DATA(MSIOF0_SCK, DU_DG0), + PINMUX_IPSR_DATA(MSIOF0_SCK, VI0_DATA16), + PINMUX_IPSR_IDATA(MSIOF0_SYNC), + PINMUX_IPSR_DATA(MSIOF0_SYNC, DU_DG1), + PINMUX_IPSR_DATA(MSIOF0_SYNC, VI0_DATA17), + PINMUX_IPSR_IDATA(MSIOF0_SS1), + PINMUX_IPSR_DATA(MSIOF0_SS1, DU_DB0), + PINMUX_IPSR_DATA(MSIOF0_SS1, TCLK3), + PINMUX_IPSR_DATA(MSIOF0_SS1, VI0_DATA18), + PINMUX_IPSR_IDATA(MSIOF0_SS2), + PINMUX_IPSR_DATA(MSIOF0_SS2, DU_DB1), + PINMUX_IPSR_DATA(MSIOF0_SS2, TCLK4), + PINMUX_IPSR_DATA(MSIOF0_SS2, VI0_DATA19), + + /* IPSR10 */ + PINMUX_IPSR_IDATA(SCL3), + PINMUX_IPSR_DATA(SCL3, VI0_DATA20), + PINMUX_IPSR_IDATA(SDA3), + PINMUX_IPSR_DATA(SDA3, VI0_DATA21), + PINMUX_IPSR_IDATA(FSO_CFE_0_N), + PINMUX_IPSR_DATA(FSO_CFE_0_N, VI0_DATA22), + PINMUX_IPSR_IDATA(FSO_CFE_1_N), + PINMUX_IPSR_DATA(FSO_CFE_1_N, VI0_DATA23), + PINMUX_IPSR_IDATA(FSO_TOE_N), +}; + +static struct pinmux_gpio pinmux_gpios[] = { + PINMUX_GPIO_GP_ALL(), + + /* GPSR0 */ + GPIO_GFN(DU_EXODDF_DU_ODDF_DISP_CDE), + GPIO_GFN(DU_EXVSYNC_DU_VSYNC), + GPIO_GFN(DU_EXHSYNC_DU_HSYNC), + GPIO_GFN(DU_DOTCLKOUT), + GPIO_GFN(DU_DB7), + GPIO_GFN(DU_DB6), + GPIO_GFN(DU_DB5), + GPIO_GFN(DU_DB4), + GPIO_GFN(DU_DB3), + GPIO_GFN(DU_DB2), + GPIO_GFN(DU_DG7), + GPIO_GFN(DU_DG6), + GPIO_GFN(DU_DG5), + GPIO_GFN(DU_DG4), + GPIO_GFN(DU_DG3), + GPIO_GFN(DU_DG2), + GPIO_GFN(DU_DR7), + GPIO_GFN(DU_DR6), + GPIO_GFN(DU_DR5), + GPIO_GFN(DU_DR4), + GPIO_GFN(DU_DR3), + GPIO_GFN(DU_DR2), + + /* GPSR1 */ + GPIO_GFN(DIGRF_CLKOUT), + GPIO_GFN(DIGRF_CLKIN), + GPIO_GFN(CANFD_CLK_A), + GPIO_GFN(CANFD1_RX), + GPIO_GFN(CANFD1_TX), + GPIO_GFN(CANFD0_RX_A), + GPIO_GFN(CANFD0_TX_A), + GPIO_GFN(AVB0_AVTP_CAPTURE), + GPIO_GFN(AVB0_AVTP_MATCH), + GPIO_FN(AVB0_LINK), + GPIO_FN(AVB0_PHY_INT), + GPIO_FN(AVB0_MAGIC), + GPIO_FN(AVB0_MDC), + GPIO_FN(AVB0_MDIO), + GPIO_FN(AVB0_TXCREFCLK), + GPIO_FN(AVB0_TD3), + GPIO_FN(AVB0_TD2), + GPIO_FN(AVB0_TD1), + GPIO_FN(AVB0_TD0), + GPIO_FN(AVB0_TXC), + GPIO_FN(AVB0_TX_CTL), + GPIO_FN(AVB0_RD3), + GPIO_FN(AVB0_RD2), + GPIO_FN(AVB0_RD1), + GPIO_FN(AVB0_RD0), + GPIO_FN(AVB0_RXC), + GPIO_FN(AVB0_RX_CTL), + GPIO_GFN(IRQ0), + + /* GPSR2 */ + GPIO_GFN(FSO_TOE_N), + GPIO_GFN(FSO_CFE_1_N), + GPIO_GFN(FSO_CFE_0_N), + GPIO_GFN(SDA3), + GPIO_GFN(SCL3), + GPIO_GFN(MSIOF0_SS2), + GPIO_GFN(MSIOF0_SS1), + GPIO_GFN(MSIOF0_SYNC), + GPIO_GFN(MSIOF0_SCK), + GPIO_GFN(MSIOF0_TXD), + GPIO_GFN(MSIOF0_RXD), + GPIO_GFN(IRQ5), + GPIO_GFN(IRQ4), + GPIO_GFN(VI0_FIELD), + GPIO_GFN(VI0_DATA11), + GPIO_GFN(VI0_DATA10), + GPIO_GFN(VI0_DATA9), + GPIO_GFN(VI0_DATA8), + GPIO_GFN(VI0_DATA7), + GPIO_GFN(VI0_DATA6), + GPIO_GFN(VI0_DATA5), + GPIO_GFN(VI0_DATA4), + GPIO_GFN(VI0_DATA3), + GPIO_GFN(VI0_DATA2), + GPIO_GFN(VI0_DATA1), + GPIO_GFN(VI0_DATA0), + GPIO_GFN(VI0_VSYNC_N), + GPIO_GFN(VI0_HSYNC_N), + GPIO_GFN(VI0_CLKENB), + GPIO_GFN(VI0_CLK), + + /* GPSR3 */ + GPIO_GFN(VI1_FIELD), + GPIO_GFN(VI1_DATA11), + GPIO_GFN(VI1_DATA10), + GPIO_GFN(VI1_DATA9), + GPIO_GFN(VI1_DATA8), + GPIO_GFN(VI1_DATA7), + GPIO_GFN(VI1_DATA6), + GPIO_GFN(VI1_DATA5), + GPIO_GFN(VI1_DATA4), + GPIO_GFN(VI1_DATA3), + GPIO_GFN(VI1_DATA2), + GPIO_GFN(VI1_DATA1), + GPIO_GFN(VI1_DATA0), + GPIO_GFN(VI1_VSYNC_N), + GPIO_GFN(VI1_HSYNC_N), + GPIO_GFN(VI1_CLKENB), + GPIO_GFN(VI1_CLK), + + /* GPSR4 */ + GPIO_FN(GETHER_LINK_A), + GPIO_FN(GETHER_PHY_INT_A), + GPIO_FN(GETHER_MAGIC), + GPIO_FN(GETHER_MDC_A), + GPIO_FN(GETHER_MDIO_A), + GPIO_FN(GETHER_TXCREFCLK_MEGA), + GPIO_FN(GETHER_TXCREFCLK), + GPIO_FN(GETHER_TD3), + GPIO_FN(GETHER_TD2), + GPIO_FN(GETHER_TD1), + GPIO_FN(GETHER_TD0), + GPIO_FN(GETHER_TXC), + GPIO_FN(GETHER_TX_CTL), + GPIO_FN(GETHER_RD3), + GPIO_FN(GETHER_RD2), + GPIO_FN(GETHER_RD1), + GPIO_FN(GETHER_RD0), + GPIO_FN(GETHER_RXC), + GPIO_FN(GETHER_RX_CTL), + GPIO_GFN(SDA2), + GPIO_GFN(SCL2), + GPIO_GFN(SDA1), + GPIO_GFN(SCL1), + GPIO_GFN(SDA0), + GPIO_GFN(SCL0), + + /* GPSR5 */ + GPIO_FN(RPC_INT_N), + GPIO_FN(RPC_WP_N), + GPIO_FN(RPC_RESET_N), + GPIO_FN(QSPI1_SSL), + GPIO_FN(QSPI1_IO3), + GPIO_FN(QSPI1_IO2), + GPIO_FN(QSPI1_MISO_IO1), + GPIO_FN(QSPI1_MOSI_IO0), + GPIO_FN(QSPI1_SPCLK), + GPIO_FN(QSPI0_SSL), + GPIO_FN(QSPI0_IO3), + GPIO_FN(QSPI0_IO2), + GPIO_FN(QSPI0_MISO_IO1), + GPIO_FN(QSPI0_MOSI_IO0), + GPIO_FN(QSPI0_SPCLK), + + /* IPSR0 */ + GPIO_IFN(DU_DR2), + GPIO_FN(SCK4), + GPIO_FN(GETHER_RMII_CRS_DV), + GPIO_FN(A0), + GPIO_IFN(DU_DR3), + GPIO_FN(RX4), + GPIO_FN(GETHER_RMII_RX_ER), + GPIO_FN(A1), + GPIO_IFN(DU_DR4), + GPIO_FN(TX4), + GPIO_FN(GETHER_RMII_RXD0), + GPIO_FN(A2), + GPIO_IFN(DU_DR5), + GPIO_FN(CTS4_N), + GPIO_FN(GETHER_RMII_RXD1), + GPIO_FN(A3), + GPIO_IFN(DU_DR6), + GPIO_FN(RTS4_N_TANS), + GPIO_FN(GETHER_RMII_TXD_EN), + GPIO_FN(A4), + GPIO_IFN(DU_DR7), + GPIO_FN(GETHER_RMII_TXD0), + GPIO_FN(A5), + GPIO_IFN(DU_DG2), + GPIO_FN(GETHER_RMII_TXD1), + GPIO_FN(A6), + GPIO_IFN(DU_DG3), + GPIO_FN(CPG_CPCKOUT), + GPIO_FN(GETHER_RMII_REFCLK), + GPIO_FN(A7), + GPIO_FN(PWMFSW0), + + /* IPSR1 */ + GPIO_IFN(DU_DG4), + GPIO_FN(SCL5), + GPIO_FN(A8), + GPIO_IFN(DU_DG5), + GPIO_FN(SDA5), + GPIO_FN(GETHER_MDC_B), + GPIO_FN(A9), + GPIO_IFN(DU_DG6), + GPIO_FN(SCIF_CLK_A), + GPIO_FN(GETHER_MDIO_B), + GPIO_FN(A10), + GPIO_IFN(DU_DG7), + GPIO_FN(HRX0_A), + GPIO_FN(A11), + GPIO_IFN(DU_DB2), + GPIO_FN(HSCK0_A), + GPIO_FN(A12), + GPIO_FN(IRQ1), + GPIO_IFN(DU_DB3), + GPIO_FN(HRTS0_N_A), + GPIO_FN(A13), + GPIO_FN(IRQ2), + GPIO_IFN(DU_DB4), + GPIO_FN(HCTS0_N_A), + GPIO_FN(A14), + GPIO_FN(IRQ3), + GPIO_IFN(DU_DB5), + GPIO_FN(HTX0_A), + GPIO_FN(PWM0_A), + GPIO_FN(A15), + + /* IPSR2 */ + GPIO_IFN(DU_DB6), + GPIO_FN(MSIOF3_RXD), + GPIO_FN(A16), + GPIO_IFN(DU_DB7), + GPIO_FN(MSIOF3_TXD), + GPIO_FN(A17), + GPIO_IFN(DU_DOTCLKOUT), + GPIO_FN(MSIOF3_SS1), + GPIO_FN(GETHER_LINK_B), + GPIO_FN(A18), + GPIO_IFN(DU_EXHSYNC_DU_HSYNC), + GPIO_FN(MSIOF3_SS2), + GPIO_FN(GETHER_PHY_INT_B), + GPIO_FN(A19), + GPIO_FN(FXR_TXENA_N), + GPIO_IFN(DU_EXVSYNC_DU_VSYNC), + GPIO_FN(MSIOF3_SCK), + GPIO_FN(FXR_TXENB_N), + GPIO_IFN(DU_EXODDF_DU_ODDF_DISP_CDE), + GPIO_FN(MSIOF3_SYNC), + GPIO_IFN(IRQ0), + GPIO_FN(CC5_OSCOUT), + GPIO_IFN(VI0_CLK), + GPIO_FN(MSIOF2_SCK), + GPIO_FN(SCK3), + GPIO_FN(HSCK3), + + /* IPSR3 */ + GPIO_IFN(VI0_CLKENB), + GPIO_FN(MSIOF2_RXD), + GPIO_FN(RX3), + GPIO_FN(RD_WR_N), + GPIO_FN(HCTS3_N), + GPIO_IFN(VI0_HSYNC_N), + GPIO_FN(MSIOF2_TXD), + GPIO_FN(TX3), + GPIO_FN(HRTS3_N), + GPIO_IFN(VI0_VSYNC_N), + GPIO_FN(MSIOF2_SYNC), + GPIO_FN(CTS3_N), + GPIO_FN(HTX3), + GPIO_IFN(VI0_DATA0), + GPIO_FN(MSIOF2_SS1), + GPIO_FN(RTS3_N_TANS), + GPIO_FN(HRX3), + GPIO_IFN(VI0_DATA1), + GPIO_FN(MSIOF2_SS2), + GPIO_FN(SCK1), + GPIO_FN(SPEEDIN_A), + GPIO_IFN(VI0_DATA2), + GPIO_FN(AVB0_AVTP_PPS), + GPIO_IFN(VI0_DATA3), + GPIO_FN(HSCK1), + GPIO_IFN(VI0_DATA4), + GPIO_FN(HRTS1_N), + GPIO_FN(RX1_A), + + /* IPSR4 */ + GPIO_IFN(VI0_DATA5), + GPIO_FN(HCTS1_N), + GPIO_FN(TX1_A), + GPIO_IFN(VI0_DATA6), + GPIO_FN(HTX1), + GPIO_FN(CTS1_N), + GPIO_IFN(VI0_DATA7), + GPIO_FN(HRX1), + GPIO_FN(RTS1_N_TANS), + GPIO_IFN(VI0_DATA8), + GPIO_FN(HSCK2), + GPIO_IFN(VI0_DATA9), + GPIO_FN(HCTS2_N), + GPIO_FN(PWM1_A), + GPIO_FN(FSO_CFE_0_N_B), + GPIO_IFN(VI0_DATA10), + GPIO_FN(HRTS2_N), + GPIO_FN(PWM2_A), + GPIO_IFN(VI0_DATA11), + GPIO_FN(HTX2), + GPIO_FN(PWM3_A), + GPIO_IFN(VI0_FIELD), + GPIO_FN(HRX2), + GPIO_FN(PWM4_A), + GPIO_FN(CS1_N), + GPIO_FN(FSCLKST2_N_A), + + /* IPSR5 */ + GPIO_IFN(VI1_CLK), + GPIO_FN(MSIOF1_RXD), + GPIO_FN(CS0_N), + GPIO_IFN(VI1_CLKENB), + GPIO_FN(MSIOF1_TXD), + GPIO_FN(D0), + GPIO_IFN(VI1_HSYNC_N), + GPIO_FN(MSIOF1_SCK), + GPIO_FN(D1), + GPIO_IFN(VI1_VSYNC_N), + GPIO_FN(MSIOF1_SYNC), + GPIO_FN(D2), + GPIO_IFN(VI1_DATA0), + GPIO_FN(MSIOF1_SS1), + GPIO_FN(D3), + GPIO_FN(MMC_WP), + GPIO_IFN(VI1_DATA1), + GPIO_FN(MSIOF1_SS2), + GPIO_FN(D4), + GPIO_FN(MMC_CD), + GPIO_IFN(VI1_DATA2), + GPIO_FN(CANFD0_TX_B), + GPIO_FN(D5), + GPIO_FN(MMC_DS), + GPIO_IFN(VI1_DATA3), + GPIO_FN(CANFD0_RX_B), + GPIO_FN(D6), + GPIO_FN(MMC_CMD), + + /* IPSR6 */ + GPIO_IFN(VI1_DATA4), + GPIO_FN(CANFD_CLK_B), + GPIO_FN(D7), + GPIO_FN(MMC_D0), + GPIO_IFN(VI1_DATA5), + GPIO_FN(D8), + GPIO_FN(MMC_D1), + GPIO_IFN(VI1_DATA6), + GPIO_FN(D9), + GPIO_FN(MMC_D2), + GPIO_IFN(VI1_DATA7), + GPIO_FN(D10), + GPIO_FN(MMC_D3), + GPIO_IFN(VI1_DATA8), + GPIO_FN(D11), + GPIO_FN(MMC_CLK), + GPIO_IFN(VI1_DATA9), + GPIO_FN(TCLK1_A), + GPIO_FN(D12), + GPIO_FN(MMC_D4), + GPIO_IFN(VI1_DATA10), + GPIO_FN(TCLK2_A), + GPIO_FN(D13), + GPIO_FN(MMC_D5), + GPIO_IFN(VI1_DATA11), + GPIO_FN(SCL4), + GPIO_FN(D14), + GPIO_FN(MMC_D6), + + /* IPSR7 */ + GPIO_IFN(VI1_FIELD), + GPIO_FN(SDA4), + GPIO_FN(D15), + GPIO_FN(MMC_D7), + GPIO_IFN(SCL0), + GPIO_FN(CLKOUT), + GPIO_IFN(SDA0), + GPIO_FN(BS_N), + GPIO_FN(SCK0), + GPIO_FN(HSCK0_B), + GPIO_IFN(SCL1), + GPIO_FN(TPU0TO2), + GPIO_FN(RD_N), + GPIO_FN(CTS0_N), + GPIO_FN(HCTS0_N_B), + GPIO_IFN(SDA1), + GPIO_FN(TPU0TO3), + GPIO_FN(WE0_N), + GPIO_FN(RTS0_N_TANS), + GPIO_FN(HRTS0_N_B), + GPIO_IFN(SCL2), + GPIO_FN(WE1_N), + GPIO_FN(RX0), + GPIO_FN(HRX0_B), + GPIO_IFN(SDA2), + GPIO_FN(EX_WAIT0), + GPIO_FN(TX0), + GPIO_FN(HTX0_B), + GPIO_IFN(AVB0_AVTP_MATCH), + GPIO_FN(TPU0TO0), + + /* IPSR8 */ + GPIO_IFN(AVB0_AVTP_CAPTURE), + GPIO_FN(TPU0TO1), + GPIO_IFN(CANFD0_TX_A), + GPIO_FN(FXR_TXDA), + GPIO_FN(PWM0_B), + GPIO_FN(DU_DISP), + GPIO_IFN(CANFD0_RX_A), + GPIO_FN(RXDA_EXTFXR), + GPIO_FN(PWM1_B), + GPIO_FN(DU_CDE), + GPIO_IFN(CANFD1_TX), + GPIO_FN(FXR_TXDB), + GPIO_FN(PWM2_B), + GPIO_FN(TCLK1_B), + GPIO_FN(TX1_B), + GPIO_IFN(CANFD1_RX), + GPIO_FN(RXDB_EXTFXR), + GPIO_FN(PWM3_B), + GPIO_FN(TCLK2_B), + GPIO_FN(RX1_B), + GPIO_IFN(CANFD_CLK_A), + GPIO_FN(CLK_EXTFXR), + GPIO_FN(PWM4_B), + GPIO_FN(SPEEDIN_B), + GPIO_FN(SCIF_CLK_B), + GPIO_IFN(DIGRF_CLKIN), + GPIO_FN(DIGRF_CLKEN_IN), + GPIO_IFN(DIGRF_CLKOUT), + GPIO_FN(DIGRF_CLKEN_OUT), + + /* IPSR9 */ + GPIO_IFN(IRQ4), + GPIO_FN(VI0_DATA12), + GPIO_IFN(IRQ5), + GPIO_FN(VI0_DATA13), + GPIO_IFN(MSIOF0_RXD), + GPIO_FN(DU_DR0), + GPIO_FN(VI0_DATA14), + GPIO_IFN(MSIOF0_TXD), + GPIO_FN(DU_DR1), + GPIO_FN(VI0_DATA15), + GPIO_IFN(MSIOF0_SCK), + GPIO_FN(DU_DG0), + GPIO_FN(VI0_DATA16), + GPIO_IFN(MSIOF0_SYNC), + GPIO_FN(DU_DG1), + GPIO_FN(VI0_DATA17), + GPIO_IFN(MSIOF0_SS1), + GPIO_FN(DU_DB0), + GPIO_FN(TCLK3), + GPIO_FN(VI0_DATA18), + GPIO_IFN(MSIOF0_SS2), + GPIO_FN(DU_DB1), + GPIO_FN(TCLK4), + GPIO_FN(VI0_DATA19), + + /* IPSR10 */ + GPIO_IFN(SCL3), + GPIO_FN(VI0_DATA20), + GPIO_IFN(SDA3), + GPIO_FN(VI0_DATA21), + GPIO_IFN(FSO_CFE_0_N), + GPIO_FN(VI0_DATA22), + GPIO_IFN(FSO_CFE_1_N), + GPIO_FN(VI0_DATA23), + GPIO_IFN(FSO_TOE_N), +}; + +static struct pinmux_cfg_reg pinmux_config_regs[] = { + /* GPSR0(0xE6060100) md[3:1] controls initial value */ + /* md[3:1] .. 0 : 0x0000FFFF */ + /* .. other : 0x00000000 */ + { PINMUX_CFG_REG("GPSR0", 0xE6060100, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_0_21_FN, GFN_DU_EXODDF_DU_ODDF_DISP_CDE, + GP_0_20_FN, GFN_DU_EXVSYNC_DU_VSYNC, + GP_0_19_FN, GFN_DU_EXHSYNC_DU_HSYNC, + GP_0_18_FN, GFN_DU_DOTCLKOUT, + GP_0_17_FN, GFN_DU_DB7, + GP_0_16_FN, GFN_DU_DB6, + GP_0_15_FN, GFN_DU_DB5, + GP_0_14_FN, GFN_DU_DB4, + GP_0_13_FN, GFN_DU_DB3, + GP_0_12_FN, GFN_DU_DB2, + GP_0_11_FN, GFN_DU_DG7, + GP_0_10_FN, GFN_DU_DG6, + GP_0_9_FN, GFN_DU_DG5, + GP_0_8_FN, GFN_DU_DG4, + GP_0_7_FN, GFN_DU_DG3, + GP_0_6_FN, GFN_DU_DG2, + GP_0_5_FN, GFN_DU_DR7, + GP_0_4_FN, GFN_DU_DR6, + GP_0_3_FN, GFN_DU_DR5, + GP_0_2_FN, GFN_DU_DR4, + GP_0_1_FN, GFN_DU_DR3, + GP_0_0_FN, GFN_DU_DR2 } + }, + /* GPSR1(0xE6060104) is md[3:1] controls initial value */ + /* md[3:1] .. 0 : 0x0EFFFFFF */ + /* .. other : 0x00000000 */ + { PINMUX_CFG_REG("GPSR1", 0xE6060104, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_1_27_FN, GFN_DIGRF_CLKOUT, + GP_1_26_FN, GFN_DIGRF_CLKIN, + GP_1_25_FN, GFN_CANFD_CLK_A, + GP_1_24_FN, GFN_CANFD1_RX, + GP_1_23_FN, GFN_CANFD1_TX, + GP_1_22_FN, GFN_CANFD0_RX_A, + GP_1_21_FN, GFN_CANFD0_TX_A, + GP_1_20_FN, GFN_AVB0_AVTP_CAPTURE, + GP_1_19_FN, GFN_AVB0_AVTP_MATCH, + GP_1_18_FN, FN_AVB0_LINK, + GP_1_17_FN, FN_AVB0_PHY_INT, + GP_1_16_FN, FN_AVB0_MAGIC, + GP_1_15_FN, FN_AVB0_MDC, + GP_1_14_FN, FN_AVB0_MDIO, + GP_1_13_FN, FN_AVB0_TXCREFCLK, + GP_1_12_FN, FN_AVB0_TD3, + GP_1_11_FN, FN_AVB0_TD2, + GP_1_10_FN, FN_AVB0_TD1, + GP_1_9_FN, FN_AVB0_TD0, + GP_1_8_FN, FN_AVB0_TXC, + GP_1_7_FN, FN_AVB0_TX_CTL, + GP_1_6_FN, FN_AVB0_RD3, + GP_1_5_FN, FN_AVB0_RD2, + GP_1_4_FN, FN_AVB0_RD1, + GP_1_3_FN, FN_AVB0_RD0, + GP_1_2_FN, FN_AVB0_RXC, + GP_1_1_FN, FN_AVB0_RX_CTL, + GP_1_0_FN, GFN_IRQ0 } + }, + /* GPSR2(0xE6060108) is md[3:1] controls */ + /* md[3:1] .. 0 : 0x000003C0 */ + /* .. other : 0x00000200 */ + { PINMUX_CFG_REG("GPSR2", 0xE6060108, 32, 1) { + 0, 0, + 0, 0, + GP_2_29_FN, GFN_FSO_TOE_N, + GP_2_28_FN, GFN_FSO_CFE_1_N, + GP_2_27_FN, GFN_FSO_CFE_0_N, + GP_2_26_FN, GFN_SDA3, + GP_2_25_FN, GFN_SCL3, + GP_2_24_FN, GFN_MSIOF0_SS2, + GP_2_23_FN, GFN_MSIOF0_SS1, + GP_2_22_FN, GFN_MSIOF0_SYNC, + GP_2_21_FN, GFN_MSIOF0_SCK, + GP_2_20_FN, GFN_MSIOF0_TXD, + GP_2_19_FN, GFN_MSIOF0_RXD, + GP_2_18_FN, GFN_IRQ5, + GP_2_17_FN, GFN_IRQ4, + GP_2_16_FN, GFN_VI0_FIELD, + GP_2_15_FN, GFN_VI0_DATA11, + GP_2_14_FN, GFN_VI0_DATA10, + GP_2_13_FN, GFN_VI0_DATA9, + GP_2_12_FN, GFN_VI0_DATA8, + GP_2_11_FN, GFN_VI0_DATA7, + GP_2_10_FN, GFN_VI0_DATA6, + GP_2_9_FN, GFN_VI0_DATA5, + GP_2_8_FN, GFN_VI0_DATA4, + GP_2_7_FN, GFN_VI0_DATA3, + GP_2_6_FN, GFN_VI0_DATA2, + GP_2_5_FN, GFN_VI0_DATA1, + GP_2_4_FN, GFN_VI0_DATA0, + GP_2_3_FN, GFN_VI0_VSYNC_N, + GP_2_2_FN, GFN_VI0_HSYNC_N, + GP_2_1_FN, GFN_VI0_CLKENB, + GP_2_0_FN, GFN_VI0_CLK } + }, + + /* GPSR3 */ + { PINMUX_CFG_REG("GPSR3", 0xE606010C, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_3_16_FN, GFN_VI1_FIELD, + GP_3_15_FN, GFN_VI1_DATA11, + GP_3_14_FN, GFN_VI1_DATA10, + GP_3_13_FN, GFN_VI1_DATA9, + GP_3_12_FN, GFN_VI1_DATA8, + GP_3_11_FN, GFN_VI1_DATA7, + GP_3_10_FN, GFN_VI1_DATA6, + GP_3_9_FN, GFN_VI1_DATA5, + GP_3_8_FN, GFN_VI1_DATA4, + GP_3_7_FN, GFN_VI1_DATA3, + GP_3_6_FN, GFN_VI1_DATA2, + GP_3_5_FN, GFN_VI1_DATA1, + GP_3_4_FN, GFN_VI1_DATA0, + GP_3_3_FN, GFN_VI1_VSYNC_N, + GP_3_2_FN, GFN_VI1_HSYNC_N, + GP_3_1_FN, GFN_VI1_CLKENB, + GP_3_0_FN, GFN_VI1_CLK } + }, + /* GPSR4 */ + { PINMUX_CFG_REG("GPSR4", 0xE6060110, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_4_24_FN, FN_GETHER_LINK_A, + GP_4_23_FN, FN_GETHER_PHY_INT_A, + GP_4_22_FN, FN_GETHER_MAGIC, + GP_4_21_FN, FN_GETHER_MDC_A, + GP_4_20_FN, FN_GETHER_MDIO_A, + GP_4_19_FN, FN_GETHER_TXCREFCLK_MEGA, + GP_4_18_FN, FN_GETHER_TXCREFCLK, + GP_4_17_FN, FN_GETHER_TD3, + GP_4_16_FN, FN_GETHER_TD2, + GP_4_15_FN, FN_GETHER_TD1, + GP_4_14_FN, FN_GETHER_TD0, + GP_4_13_FN, FN_GETHER_TXC, + GP_4_12_FN, FN_GETHER_TX_CTL, + GP_4_11_FN, FN_GETHER_RD3, + GP_4_10_FN, FN_GETHER_RD2, + GP_4_9_FN, FN_GETHER_RD1, + GP_4_8_FN, FN_GETHER_RD0, + GP_4_7_FN, FN_GETHER_RXC, + GP_4_6_FN, FN_GETHER_RX_CTL, + GP_4_5_FN, GFN_SDA2, + GP_4_4_FN, GFN_SCL2, + GP_4_3_FN, GFN_SDA1, + GP_4_2_FN, GFN_SCL1, + GP_4_1_FN, GFN_SDA0, + GP_4_0_FN, GFN_SCL0 } + }, + /* GPSR5 */ + { PINMUX_CFG_REG("GPSR5", 0xE6060114, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_5_14_FN, FN_RPC_INT_N, + GP_5_13_FN, FN_RPC_WP_N, + GP_5_12_FN, FN_RPC_RESET_N, + GP_5_11_FN, FN_QSPI1_SSL, + GP_5_10_FN, FN_QSPI1_IO3, + GP_5_9_FN, FN_QSPI1_IO2, + GP_5_8_FN, FN_QSPI1_MISO_IO1, + GP_5_7_FN, FN_QSPI1_MOSI_IO0, + GP_5_6_FN, FN_QSPI1_SPCLK, + GP_5_5_FN, FN_QSPI0_SSL, + GP_5_4_FN, FN_QSPI0_IO3, + GP_5_3_FN, FN_QSPI0_IO2, + GP_5_2_FN, FN_QSPI0_MISO_IO1, + GP_5_1_FN, FN_QSPI0_MOSI_IO0, + GP_5_0_FN, FN_QSPI0_SPCLK } + }, + + { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060200, 32, + 4, 4, 4, 4, 4, 4, 4, 4) { + /* IPSR0_31_28 [4] */ + IFN_DU_DG3, FN_CPG_CPCKOUT, FN_GETHER_RMII_REFCLK, FN_A7, + FN_PWMFSW0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR0_27_24 [4] */ + IFN_DU_DG2, 0, FN_GETHER_RMII_TXD1, FN_A6, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR0_23_20 [4] */ + IFN_DU_DR7, 0, FN_GETHER_RMII_TXD0, FN_A5, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR0_19_16 [4] */ + IFN_DU_DR6, FN_RTS4_N_TANS, FN_GETHER_RMII_TXD_EN, FN_A4, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR0_15_12 [4] */ + IFN_DU_DR5, FN_CTS4_N, FN_GETHER_RMII_RXD1, FN_A3, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR0_11_8 [4] */ + IFN_DU_DR4, FN_TX4, FN_GETHER_RMII_RXD0, FN_A2, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR0_7_4 [4] */ + IFN_DU_DR3, FN_RX4, FN_GETHER_RMII_RX_ER, FN_A1, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR0_3_0 [4] */ + IFN_DU_DR2, FN_SCK4, FN_GETHER_RMII_CRS_DV, FN_A0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + } + }, + { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060204, 32, + 4, 4, 4, 4, 4, 4, 4, 4) { + /* IPSR1_31_28 [4] */ + IFN_DU_DB5, FN_HTX0_A, FN_PWM0_A, FN_A15, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR1_27_24 [4] */ + IFN_DU_DB4, FN_HCTS0_N_A, 0, FN_A14, + FN_IRQ3, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR1_23_20 [4] */ + IFN_DU_DB3, FN_HRTS0_N_A, 0, FN_A13, + FN_IRQ2, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR1_19_16 [4] */ + IFN_DU_DB2, FN_HSCK0_A, 0, FN_A12, + FN_IRQ1, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR1_15_12 [4] */ + IFN_DU_DG7, FN_HRX0_A, 0, FN_A11, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR1_11_8 [4] */ + IFN_DU_DG6, FN_SCIF_CLK_A, FN_GETHER_MDIO_B, FN_A10, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR1_7_4 [4] */ + IFN_DU_DG5, FN_SDA5, FN_GETHER_MDC_B, FN_A9, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR1_3_0 [4] */ + IFN_DU_DG4, FN_SCL5, 0, FN_A8, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0 + } + }, + { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060208, 32, + 4, 4, 4, 4, 4, 4, 4, 4) { + /* IPSR2_31_28 [4] */ + IFN_VI0_CLK, FN_MSIOF2_SCK, FN_SCK3, 0, + FN_HSCK3, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR2_27_24 [4] */ + IFN_IRQ0, FN_CC5_OSCOUT, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR2_23_20 [4] */ + IFN_DU_EXODDF_DU_ODDF_DISP_CDE, FN_MSIOF3_SYNC, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR2_19_16 [4] */ + IFN_DU_EXVSYNC_DU_VSYNC, FN_MSIOF3_SCK, 0, 0, + FN_FXR_TXENB_N, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR2_15_12 [4] */ + IFN_DU_EXHSYNC_DU_HSYNC, FN_MSIOF3_SS2, FN_GETHER_PHY_INT_B, FN_A19, + FN_FXR_TXENA_N, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR2_11_8 [4] */ + IFN_DU_DOTCLKOUT, FN_MSIOF3_SS1, FN_GETHER_LINK_B, FN_A18, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR2_7_4 [4] */ + IFN_DU_DB7, FN_MSIOF3_TXD, 0, FN_A17, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR2_3_0 [4] */ + IFN_DU_DB6, FN_MSIOF3_RXD, 0, FN_A16, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + } + }, + { PINMUX_CFG_REG_VAR("IPSR3", 0xE606020C, 32, + 4, 4, 4, 4, 4, 4, 4, 4) { + /* IPSR3_31_28 [4] */ + IFN_VI0_DATA4, FN_HRTS1_N, FN_RX1_A, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR3_27_24 [4] */ + IFN_VI0_DATA3, FN_HSCK1, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR3_23_20 [4] */ + IFN_VI0_DATA2, FN_AVB0_AVTP_PPS, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR3_19_16 [4] */ + IFN_VI0_DATA1, FN_MSIOF2_SS2, FN_SCK1, 0, + FN_SPEEDIN_A, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR3_15_12 [4] */ + IFN_VI0_DATA0, FN_MSIOF2_SS1, FN_RTS3_N_TANS, 0, + FN_HRX3, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR3_11_8 [4] */ + IFN_VI0_VSYNC_N, FN_MSIOF2_SYNC, FN_CTS3_N, 0, + FN_HTX3, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR3_7_4 [4] */ + IFN_VI0_HSYNC_N, FN_MSIOF2_TXD, FN_TX3, 0, + FN_HRTS3_N, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR3_3_0 [4] */ + IFN_VI0_CLKENB, FN_MSIOF2_RXD, FN_RX3, FN_RD_WR_N, + FN_HCTS3_N, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + } + }, + { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060210, 32, + 4, 4, 4, 4, 4, 4, 4, 4) { + /* IPSR4_31_28 [4] */ + IFN_VI0_FIELD, FN_HRX2, FN_PWM4_A, FN_CS1_N, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR4_27_24 [4] */ + IFN_VI0_DATA11, FN_HTX2, FN_PWM3_A, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR4_23_20 [4] */ + IFN_VI0_DATA10, FN_HRTS2_N, FN_PWM2_A, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR4_19_16 [4] */ + IFN_VI0_DATA9, FN_HCTS2_N, FN_PWM1_A, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR4_15_12 [4] */ + IFN_VI0_DATA8, FN_HSCK2, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR4_11_8 [4] */ + IFN_VI0_DATA7, FN_HRX1, FN_RTS1_N_TANS, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR4_7_4 [4] */ + IFN_VI0_DATA6, FN_HTX1, FN_CTS1_N, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR4_3_0 [4] */ + IFN_VI0_DATA5, FN_HCTS1_N, FN_TX1_A, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + } + }, + { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060214, 32, + 4, 4, 4, 4, 4, 4, 4, 4) { + /* IPSR5_31_28 [4] */ + IFN_VI1_DATA3, FN_CANFD0_RX_B, 0, FN_D6, + FN_MMC_CMD, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR5_27_24 [4] */ + IFN_VI1_DATA2, FN_CANFD0_TX_B, 0, FN_D5, + FN_MMC_DS, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR5_23_20 [4] */ + IFN_VI1_DATA1, FN_MSIOF1_SS2, 0, FN_D4, + FN_MMC_CD, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR5_19_16 [4] */ + IFN_VI1_DATA0, FN_MSIOF1_SS1, 0, FN_D3, + FN_MMC_WP, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR5_15_12 [4] */ + IFN_VI1_VSYNC_N, FN_MSIOF1_SYNC, 0, FN_D2, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR5_11_8 [4] */ + IFN_VI1_HSYNC_N, FN_MSIOF1_SCK, 0, FN_D1, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR5_7_4 [4] */ + IFN_VI1_CLKENB, FN_MSIOF1_TXD, 0, FN_D0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR5_3_0 [4] */ + IFN_VI1_CLK, FN_MSIOF1_RXD, 0, FN_CS0_N, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + } + }, + { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060218, 32, + 4, 4, 4, 4, 4, 4, 4, 4) { + /* IPSR6_31_28 [4] */ + IFN_VI1_DATA11, FN_SCL4, 0, FN_D14, + FN_MMC_D6, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR6_27_24 [4] */ + IFN_VI1_DATA10, FN_TCLK2_A, 0, FN_D13, + FN_MMC_D5, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR6_23_20 [4] */ + IFN_VI1_DATA9, FN_TCLK1_A, 0, FN_D12, + FN_MMC_D4, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR6_19_16 [4] */ + IFN_VI1_DATA8, 0, 0, FN_D11, + FN_MMC_CLK, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR6_15_12 [4] */ + IFN_VI1_DATA7, 0, 0, FN_D10, + FN_MMC_D3, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR6_11_8 [4] */ + IFN_VI1_DATA6, 0, 0, FN_D9, + FN_MMC_D2, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR6_7_4 [4] */ + IFN_VI1_DATA5, 0, 0, FN_D8, + FN_MMC_D1, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR6_3_0 [4] */ + IFN_VI1_DATA4, FN_CANFD_CLK_B, 0, FN_D7, + FN_MMC_D0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + } + }, + { PINMUX_CFG_REG_VAR("IPSR7", 0xE606021C, 32, + 4, 4, 4, 4, 4, 4, 4, 4) { + /* IPSR7_31_28 [4] */ + IFN_AVB0_AVTP_MATCH, FN_TPU0TO0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR7_27_24 [4] */ + IFN_SDA2, 0, 0, FN_EX_WAIT0, + FN_TX0, FN_HTX0_B, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR7_23_20 [4] */ + IFN_SCL2, 0, 0, FN_WE1_N, + FN_RX0, FN_HRX0_B, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR7_19_16 [4] */ + IFN_SDA1, 0, FN_TPU0TO3, FN_WE0_N, + FN_RTS0_N_TANS, FN_HRTS0_N_B, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR7_15_12 [4] */ + IFN_SCL1, 0, FN_TPU0TO2, FN_RD_N, + FN_CTS0_N, FN_HCTS0_N_B, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR7_11_8 [4] */ + IFN_SDA0, 0, 0, FN_BS_N, + FN_SCK0, FN_HSCK0_B, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR7_7_4 [4] */ + IFN_SCL0, 0, 0, FN_CLKOUT, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR7_3_0 [4] */ + IFN_VI1_FIELD, FN_SDA4, 0, FN_D15, + FN_MMC_D7, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + } + }, + { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060220, 32, + 4, 4, 4, 4, 4, 4, 4, 4) { + /* IPSR8_31_28 [4] */ + IFN_DIGRF_CLKOUT, FN_DIGRF_CLKEN_OUT, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR8_27_24 [4] */ + IFN_DIGRF_CLKIN, FN_DIGRF_CLKEN_IN, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR8_23_20 [4] */ + IFN_CANFD_CLK_A, FN_CLK_EXTFXR, FN_PWM4_B, FN_SPEEDIN_B, + FN_SCIF_CLK_B, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR8_19_16 [4] */ + IFN_CANFD1_RX, FN_RXDB_EXTFXR, FN_PWM3_B, FN_TCLK2_B, + FN_RX1_B, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR8_15_12 [4] */ + IFN_CANFD1_TX, FN_FXR_TXDB, FN_PWM2_B, FN_TCLK1_B, + FN_TX1_B, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR8_11_8 [4] */ + IFN_CANFD0_RX_A, FN_RXDA_EXTFXR, FN_PWM1_B, FN_DU_CDE, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR8_7_4 [4] */ + IFN_CANFD0_TX_A, FN_FXR_TXDA, FN_PWM0_B, FN_DU_DISP, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR8_3_0 [4] */ + IFN_AVB0_AVTP_CAPTURE, FN_TPU0TO1, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + } + }, + { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060224, 32, + 4, 4, 4, 4, 4, 4, 4, 4) { + /* IPSR9_31_28 [4] */ + IFN_MSIOF0_SS2, FN_DU_DB1, FN_TCLK4, FN_VI0_DATA19, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR9_27_24 [4] */ + IFN_MSIOF0_SS1, FN_DU_DB0, FN_TCLK3, FN_VI0_DATA18, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR9_23_20 [4] */ + IFN_MSIOF0_SYNC, FN_DU_DG1, 0, FN_VI0_DATA17, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR9_19_16 [4] */ + IFN_MSIOF0_SCK, FN_DU_DG0, 0, FN_VI0_DATA16, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR9_15_12 [4] */ + IFN_MSIOF0_TXD, FN_DU_DR1, 0, FN_VI0_DATA15, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR9_11_8 [4] */ + IFN_MSIOF0_RXD, FN_DU_DR0, 0, FN_VI0_DATA14, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR9_7_4 [4] */ + IFN_IRQ5, 0, 0, FN_VI0_DATA13, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR9_3_0 [4] */ + IFN_IRQ4, 0, 0, FN_VI0_DATA12, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + } + }, + { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060228, 32, + 4, 4, 4, 4, 4, 4, 4, 4) { + /* IPSR10_31_28 [4] */ + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR10_27_24 [4] */ + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR10_23_20 [4] */ + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR10_19_16 [4] */ + IFN_FSO_TOE_N, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR10_15_12 [4] */ + IFN_FSO_CFE_1_N, 0, 0, FN_VI0_DATA23, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR10_11_8 [4] */ + IFN_FSO_CFE_0_N, 0, 0, FN_VI0_DATA22, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR10_7_4 [4] */ + IFN_SDA3, 0, 0, FN_VI0_DATA21, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + /* IPSR10_3_0 [4] */ + IFN_SCL3, 0, 0, FN_VI0_DATA20, + 0, 0, 0, 0, + 0, 0, 0, 0, + 0, 0, 0, 0, + } + }, + { PINMUX_CFG_REG("MOD_SEL0", 0xE6060500, 32, 1) { + /* reserved [31..24] */ + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + /* reserved [23..16] */ + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + /* reserved [15..11] */ + 0, 0, + 0, 0, + 0, 0, + 0, 0, + /* SEL_CANFD0 [1] */ + FN_SEL_CANFD0_0, + FN_SEL_CANFD0_1, + /* SEL_GETHER [1] */ + FN_SEL_GETHER_0, + FN_SEL_GETHER_1, + /* SEL_HSCIF0 [1] */ + FN_SEL_HSCIF0_0, + FN_SEL_HSCIF0_1, + /* SEL_PWM4 [1] */ + FN_SEL_PWM0_0, + FN_SEL_PWM0_1, + /* SEL_PWM3 [1] */ + FN_SEL_PWM1_0, + FN_SEL_PWM1_1, + /* SEL_PWM2 [1] */ + FN_SEL_PWM2_0, + FN_SEL_PWM2_1, + /* SEL_PWM1 [1] */ + FN_SEL_PWM3_0, + FN_SEL_PWM3_1, + /* SEL_PWM0 [1] */ + FN_SEL_PWM4_0, + FN_SEL_PWM4_1, + 0, 0, + /* SEL_RSP [1] */ + FN_SEL_RSP_0, + FN_SEL_RSP_1, + /* SEL_SCIF1 [1] */ + FN_SEL_SCIF1_0, + FN_SEL_SCIF1_1, + /* SEL_TMU [1] */ + FN_SEL_TMU_0, + FN_SEL_TMU_1, + } + }, + + /* under construction */ + { PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_0_21_IN, GP_0_21_OUT, + GP_0_20_IN, GP_0_20_OUT, + GP_0_19_IN, GP_0_19_OUT, + GP_0_18_IN, GP_0_18_OUT, + GP_0_17_IN, GP_0_17_OUT, + GP_0_16_IN, GP_0_16_OUT, + GP_0_15_IN, GP_0_15_OUT, + GP_0_14_IN, GP_0_14_OUT, + GP_0_13_IN, GP_0_13_OUT, + GP_0_12_IN, GP_0_12_OUT, + GP_0_11_IN, GP_0_11_OUT, + GP_0_10_IN, GP_0_10_OUT, + GP_0_9_IN, GP_0_9_OUT, + GP_0_8_IN, GP_0_8_OUT, + GP_0_7_IN, GP_0_7_OUT, + GP_0_6_IN, GP_0_6_OUT, + GP_0_5_IN, GP_0_5_OUT, + GP_0_4_IN, GP_0_4_OUT, + GP_0_3_IN, GP_0_3_OUT, + GP_0_2_IN, GP_0_2_OUT, + GP_0_1_IN, GP_0_1_OUT, + GP_0_0_IN, GP_0_0_OUT, + } + }, + { PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_1_27_IN, GP_1_27_OUT, + GP_1_26_IN, GP_1_26_OUT, + GP_1_25_IN, GP_1_25_OUT, + GP_1_24_IN, GP_1_24_OUT, + GP_1_23_IN, GP_1_23_OUT, + GP_1_22_IN, GP_1_22_OUT, + GP_1_21_IN, GP_1_21_OUT, + GP_1_20_IN, GP_1_20_OUT, + GP_1_19_IN, GP_1_19_OUT, + GP_1_18_IN, GP_1_18_OUT, + GP_1_17_IN, GP_1_17_OUT, + GP_1_16_IN, GP_1_16_OUT, + GP_1_15_IN, GP_1_15_OUT, + GP_1_14_IN, GP_1_14_OUT, + GP_1_13_IN, GP_1_13_OUT, + GP_1_12_IN, GP_1_12_OUT, + GP_1_11_IN, GP_1_11_OUT, + GP_1_10_IN, GP_1_10_OUT, + GP_1_9_IN, GP_1_9_OUT, + GP_1_8_IN, GP_1_8_OUT, + GP_1_7_IN, GP_1_7_OUT, + GP_1_6_IN, GP_1_6_OUT, + GP_1_5_IN, GP_1_5_OUT, + GP_1_4_IN, GP_1_4_OUT, + GP_1_3_IN, GP_1_3_OUT, + GP_1_2_IN, GP_1_2_OUT, + GP_1_1_IN, GP_1_1_OUT, + GP_1_0_IN, GP_1_0_OUT, + } + }, + { PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) { + 0, 0, + 0, 0, + GP_2_29_IN, GP_2_29_OUT, + GP_2_28_IN, GP_2_28_OUT, + GP_2_27_IN, GP_2_27_OUT, + GP_2_26_IN, GP_2_26_OUT, + GP_2_25_IN, GP_2_25_OUT, + GP_2_24_IN, GP_2_24_OUT, + GP_2_23_IN, GP_2_23_OUT, + GP_2_22_IN, GP_2_22_OUT, + GP_2_21_IN, GP_2_21_OUT, + GP_2_20_IN, GP_2_20_OUT, + GP_2_19_IN, GP_2_19_OUT, + GP_2_18_IN, GP_2_18_OUT, + GP_2_17_IN, GP_2_17_OUT, + GP_2_16_IN, GP_2_16_OUT, + GP_2_15_IN, GP_2_15_OUT, + GP_2_14_IN, GP_2_14_OUT, + GP_2_13_IN, GP_2_13_OUT, + GP_2_12_IN, GP_2_12_OUT, + GP_2_11_IN, GP_2_11_OUT, + GP_2_10_IN, GP_2_10_OUT, + GP_2_9_IN, GP_2_9_OUT, + GP_2_8_IN, GP_2_8_OUT, + GP_2_7_IN, GP_2_7_OUT, + GP_2_6_IN, GP_2_6_OUT, + GP_2_5_IN, GP_2_5_OUT, + GP_2_4_IN, GP_2_4_OUT, + GP_2_3_IN, GP_2_3_OUT, + GP_2_2_IN, GP_2_2_OUT, + GP_2_1_IN, GP_2_1_OUT, + GP_2_0_IN, GP_2_0_OUT, + } + }, + { PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_3_16_IN, GP_3_16_OUT, + GP_3_15_IN, GP_3_15_OUT, + GP_3_14_IN, GP_3_14_OUT, + GP_3_13_IN, GP_3_13_OUT, + GP_3_12_IN, GP_3_12_OUT, + GP_3_11_IN, GP_3_11_OUT, + GP_3_10_IN, GP_3_10_OUT, + GP_3_9_IN, GP_3_9_OUT, + GP_3_8_IN, GP_3_8_OUT, + GP_3_7_IN, GP_3_7_OUT, + GP_3_6_IN, GP_3_6_OUT, + GP_3_5_IN, GP_3_5_OUT, + GP_3_4_IN, GP_3_4_OUT, + GP_3_3_IN, GP_3_3_OUT, + GP_3_2_IN, GP_3_2_OUT, + GP_3_1_IN, GP_3_1_OUT, + GP_3_0_IN, GP_3_0_OUT, + } + }, + { PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + GP_4_24_IN, GP_4_24_OUT, + GP_4_23_IN, GP_4_23_OUT, + GP_4_22_IN, GP_4_22_OUT, + GP_4_21_IN, GP_4_21_OUT, + GP_4_20_IN, GP_4_20_OUT, + GP_4_19_IN, GP_4_19_OUT, + GP_4_18_IN, GP_4_18_OUT, + GP_4_17_IN, GP_4_17_OUT, + GP_4_16_IN, GP_4_16_OUT, + GP_4_15_IN, GP_4_15_OUT, + GP_4_14_IN, GP_4_14_OUT, + GP_4_13_IN, GP_4_13_OUT, + GP_4_12_IN, GP_4_12_OUT, + GP_4_11_IN, GP_4_11_OUT, + GP_4_10_IN, GP_4_10_OUT, + GP_4_9_IN, GP_4_9_OUT, + GP_4_8_IN, GP_4_8_OUT, + GP_4_7_IN, GP_4_7_OUT, + GP_4_6_IN, GP_4_6_OUT, + GP_4_5_IN, GP_4_5_OUT, + GP_4_4_IN, GP_4_4_OUT, + GP_4_3_IN, GP_4_3_OUT, + GP_4_2_IN, GP_4_2_OUT, + GP_4_1_IN, GP_4_1_OUT, + GP_4_0_IN, GP_4_0_OUT, + } + }, + { PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) { + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + 0, 0, + + 0, 0, + GP_5_14_IN, GP_5_14_OUT, + GP_5_13_IN, GP_5_13_OUT, + GP_5_12_IN, GP_5_12_OUT, + GP_5_11_IN, GP_5_11_OUT, + GP_5_10_IN, GP_5_10_OUT, + GP_5_9_IN, GP_5_9_OUT, + GP_5_8_IN, GP_5_8_OUT, + GP_5_7_IN, GP_5_7_OUT, + GP_5_6_IN, GP_5_6_OUT, + GP_5_5_IN, GP_5_5_OUT, + GP_5_4_IN, GP_5_4_OUT, + GP_5_3_IN, GP_5_3_OUT, + GP_5_2_IN, GP_5_2_OUT, + GP_5_1_IN, GP_5_1_OUT, + GP_5_0_IN, GP_5_0_OUT, + } + }, + { }, + { }, + { }, +}; + +static struct pinmux_data_reg pinmux_data_regs[] = { + /* use OUTDT registers? */ + { PINMUX_DATA_REG("INDT0", 0xE6050008, 32) { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, GP_0_21_DATA, GP_0_20_DATA, + GP_0_19_DATA, GP_0_18_DATA, GP_0_17_DATA, GP_0_16_DATA, + GP_0_15_DATA, GP_0_14_DATA, GP_0_13_DATA, GP_0_12_DATA, + GP_0_11_DATA, GP_0_10_DATA, GP_0_9_DATA, GP_0_8_DATA, + GP_0_7_DATA, GP_0_6_DATA, GP_0_5_DATA, GP_0_4_DATA, + GP_0_3_DATA, GP_0_2_DATA, GP_0_1_DATA, GP_0_0_DATA } + }, + { PINMUX_DATA_REG("INDT1", 0xE6051008, 32) { + 0, 0, 0, 0, + GP_1_27_DATA, GP_1_26_DATA, GP_1_25_DATA, GP_1_24_DATA, + GP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA, + GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA, + GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA, + GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA, + GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA, + GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA } + }, + { PINMUX_DATA_REG("INDT2", 0xE6052008, 32) { + 0, 0, GP_2_29_DATA, GP_2_28_DATA, + GP_2_27_DATA, GP_2_26_DATA, GP_2_25_DATA, GP_2_24_DATA, + GP_2_23_DATA, GP_2_22_DATA, GP_2_21_DATA, GP_2_20_DATA, + GP_2_19_DATA, GP_2_18_DATA, GP_2_17_DATA, GP_2_16_DATA, + GP_2_15_DATA, GP_2_14_DATA, GP_2_13_DATA, GP_2_12_DATA, + GP_2_11_DATA, GP_2_10_DATA, GP_2_9_DATA, GP_2_8_DATA, + GP_2_7_DATA, GP_2_6_DATA, GP_2_5_DATA, GP_2_4_DATA, + GP_2_3_DATA, GP_2_2_DATA, GP_2_1_DATA, GP_2_0_DATA } + }, + { PINMUX_DATA_REG("INDT3", 0xE6053008, 32) { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, GP_3_16_DATA, + GP_3_15_DATA, GP_3_14_DATA, GP_3_13_DATA, GP_3_12_DATA, + GP_3_11_DATA, GP_3_10_DATA, GP_3_9_DATA, GP_3_8_DATA, + GP_3_7_DATA, GP_3_6_DATA, GP_3_5_DATA, GP_3_4_DATA, + GP_3_3_DATA, GP_3_2_DATA, GP_3_1_DATA, GP_3_0_DATA } + }, + { PINMUX_DATA_REG("INDT4", 0xE6054008, 32) { + 0, 0, 0, 0, 0, 0, 0, GP_4_24_DATA, + GP_4_23_DATA, GP_4_22_DATA, GP_4_21_DATA, GP_4_20_DATA, + GP_4_19_DATA, GP_4_18_DATA, GP_4_17_DATA, GP_4_16_DATA, + GP_4_15_DATA, GP_4_14_DATA, GP_4_13_DATA, GP_4_12_DATA, + GP_4_11_DATA, GP_4_10_DATA, GP_4_9_DATA, GP_4_8_DATA, + GP_4_7_DATA, GP_4_6_DATA, GP_4_5_DATA, GP_4_4_DATA, + GP_4_3_DATA, GP_4_2_DATA, GP_4_1_DATA, GP_4_0_DATA } + }, + { PINMUX_DATA_REG("INDT5", 0xE6055008, 32) { + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, GP_5_14_DATA, GP_5_13_DATA, GP_5_12_DATA, + GP_5_11_DATA, GP_5_10_DATA, GP_5_9_DATA, GP_5_8_DATA, + GP_5_7_DATA, GP_5_6_DATA, GP_5_5_DATA, GP_5_4_DATA, + GP_5_3_DATA, GP_5_2_DATA, GP_5_1_DATA, GP_5_0_DATA } + }, + { }, + { }, + { }, +}; + +static struct pinmux_info r8a7798_pinmux_info = { + .name = "r8a7798_pfc", + + .unlock_reg = 0xe6060000, /* PMMR */ + + .reserved_id = PINMUX_RESERVED, + .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END }, + .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END }, + .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END }, + .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END }, + .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END }, + + .first_gpio = GPIO_GP_0_0, + .last_gpio = GPIO_IFN_FSO_TOE_N, + + .gpios = pinmux_gpios, + .cfg_regs = pinmux_config_regs, + .data_regs = pinmux_data_regs, + + .gpio_data = pinmux_data, + .gpio_data_size = ARRAY_SIZE(pinmux_data), +}; + +void r8a7798_pinmux_init(void) +{ + register_pinmux(&r8a7798_pinmux_info); +} diff --git a/arch/arm/cpu/armv8/rcar_gen3/pfc.c b/arch/arm/cpu/armv8/rcar_gen3/pfc.c index bd3aa0a..72c5482 100644 --- a/arch/arm/cpu/armv8/rcar_gen3/pfc.c +++ b/arch/arm/cpu/armv8/rcar_gen3/pfc.c @@ -22,5 +22,7 @@ void pinmux_init(void) r8a7796_pinmux_init(); #elif defined(CONFIG_R8A7797) r8a7797_pinmux_init(); +#elif defined(CONFIG_R8A7798) + r8a7798_pinmux_init(); #endif } diff --git a/arch/arm/include/asm/arch-rcar_gen3/gpio.h b/arch/arm/include/asm/arch-rcar_gen3/gpio.h index fb8b758..cc94b5c 100644 --- a/arch/arm/include/asm/arch-rcar_gen3/gpio.h +++ b/arch/arm/include/asm/arch-rcar_gen3/gpio.h @@ -18,6 +18,8 @@ #include #elif defined(CONFIG_R8A7797) #include +#elif defined(CONFIG_R8A7798) +#include #endif #if defined(CONFIG_R8A7795) @@ -27,6 +29,8 @@ void r8a7795_es_pinmux_init(void); void r8a7796_pinmux_init(void); #elif defined(CONFIG_R8A7797) void r8a7797_pinmux_init(void); +#elif defined(CONFIG_R8A7798) +void r8a7798_pinmux_init(void); #endif void pinmux_init(void); diff --git a/arch/arm/include/asm/arch-rcar_gen3/r8a7798-gpio.h b/arch/arm/include/asm/arch-rcar_gen3/r8a7798-gpio.h new file mode 100644 index 0000000..8d2252f --- /dev/null +++ b/arch/arm/include/asm/arch-rcar_gen3/r8a7798-gpio.h @@ -0,0 +1,522 @@ +/* + * arch/arm/include/asm/arch-rcar_gen3/r8a7798-gpio.h + * This file defines pin function control of gpio. + * + * Copyright (C) 2018 Renesas Electronics Corp. + * Copyright (C) 2018 Cogent Embedded, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __ASM_R8A7798_GPIO_H__ +#define __ASM_R8A7798_GPIO_H__ + +/* Pin Function Controller: + * GPIO_FN_xx - GPIO used to select pin function + * GPIO_GP_x_x - GPIO mapped to real I/O pin on CPU + */ +enum { + GPIO_GP_0_0, GPIO_GP_0_1, GPIO_GP_0_2, GPIO_GP_0_3, + GPIO_GP_0_4, GPIO_GP_0_5, GPIO_GP_0_6, GPIO_GP_0_7, + GPIO_GP_0_8, GPIO_GP_0_9, GPIO_GP_0_10, GPIO_GP_0_11, + GPIO_GP_0_12, GPIO_GP_0_13, GPIO_GP_0_14, GPIO_GP_0_15, + GPIO_GP_0_16, GPIO_GP_0_17, GPIO_GP_0_18, GPIO_GP_0_19, + GPIO_GP_0_20, GPIO_GP_0_21, + + GPIO_GP_1_0, GPIO_GP_1_1, GPIO_GP_1_2, GPIO_GP_1_3, + GPIO_GP_1_4, GPIO_GP_1_5, GPIO_GP_1_6, GPIO_GP_1_7, + GPIO_GP_1_8, GPIO_GP_1_9, GPIO_GP_1_10, GPIO_GP_1_11, + GPIO_GP_1_12, GPIO_GP_1_13, GPIO_GP_1_14, GPIO_GP_1_15, + GPIO_GP_1_16, GPIO_GP_1_17, GPIO_GP_1_18, GPIO_GP_1_19, + GPIO_GP_1_20, GPIO_GP_1_21, GPIO_GP_1_22, GPIO_GP_1_23, + GPIO_GP_1_24, GPIO_GP_1_25, GPIO_GP_1_26, GPIO_GP_1_27, + + GPIO_GP_2_0, GPIO_GP_2_1, GPIO_GP_2_2, GPIO_GP_2_3, + GPIO_GP_2_4, GPIO_GP_2_5, GPIO_GP_2_6, GPIO_GP_2_7, + GPIO_GP_2_8, GPIO_GP_2_9, GPIO_GP_2_10, GPIO_GP_2_11, + GPIO_GP_2_12, GPIO_GP_2_13, GPIO_GP_2_14, GPIO_GP_2_15, + GPIO_GP_2_16, GPIO_GP_2_17, GPIO_GP_2_18, GPIO_GP_2_19, + GPIO_GP_2_20, GPIO_GP_2_21, GPIO_GP_2_22, GPIO_GP_2_23, + GPIO_GP_2_24, GPIO_GP_2_25, GPIO_GP_2_26, GPIO_GP_2_27, + GPIO_GP_2_28, GPIO_GP_2_29, + + GPIO_GP_3_0, GPIO_GP_3_1, GPIO_GP_3_2, GPIO_GP_3_3, + GPIO_GP_3_4, GPIO_GP_3_5, GPIO_GP_3_6, GPIO_GP_3_7, + GPIO_GP_3_8, GPIO_GP_3_9, GPIO_GP_3_10, GPIO_GP_3_11, + GPIO_GP_3_12, GPIO_GP_3_13, GPIO_GP_3_14, GPIO_GP_3_15, + GPIO_GP_3_16, + + GPIO_GP_4_0, GPIO_GP_4_1, GPIO_GP_4_2, GPIO_GP_4_3, + GPIO_GP_4_4, GPIO_GP_4_5, GPIO_GP_4_6, GPIO_GP_4_7, + GPIO_GP_4_8, GPIO_GP_4_9, GPIO_GP_4_10, GPIO_GP_4_11, + GPIO_GP_4_12, GPIO_GP_4_13, GPIO_GP_4_14, GPIO_GP_4_15, + GPIO_GP_4_16, GPIO_GP_4_17, GPIO_GP_4_18, GPIO_GP_4_19, + GPIO_GP_4_20, GPIO_GP_4_21, GPIO_GP_4_22, GPIO_GP_4_23, + GPIO_GP_4_24, + + GPIO_GP_5_0, GPIO_GP_5_1, GPIO_GP_5_2, GPIO_GP_5_3, + GPIO_GP_5_4, GPIO_GP_5_5, GPIO_GP_5_6, GPIO_GP_5_7, + GPIO_GP_5_8, GPIO_GP_5_9, GPIO_GP_5_10, GPIO_GP_5_11, + GPIO_GP_5_12, GPIO_GP_5_13, GPIO_GP_5_14, + + /* GPSR0 */ + GPIO_GFN_DU_EXODDF_DU_ODDF_DISP_CDE, + GPIO_GFN_DU_EXVSYNC_DU_VSYNC, + GPIO_GFN_DU_EXHSYNC_DU_HSYNC, + GPIO_GFN_DU_DOTCLKOUT, + GPIO_GFN_DU_DB7, + GPIO_GFN_DU_DB6, + GPIO_GFN_DU_DB5, + GPIO_GFN_DU_DB4, + GPIO_GFN_DU_DB3, + GPIO_GFN_DU_DB2, + GPIO_GFN_DU_DG7, + GPIO_GFN_DU_DG6, + GPIO_GFN_DU_DG5, + GPIO_GFN_DU_DG4, + GPIO_GFN_DU_DG3, + GPIO_GFN_DU_DG2, + GPIO_GFN_DU_DR7, + GPIO_GFN_DU_DR6, + GPIO_GFN_DU_DR5, + GPIO_GFN_DU_DR4, + GPIO_GFN_DU_DR3, + GPIO_GFN_DU_DR2, + + /* GPSR1 */ + GPIO_GFN_DIGRF_CLKOUT, + GPIO_GFN_DIGRF_CLKIN, + GPIO_GFN_CANFD_CLK_A, + GPIO_GFN_CANFD1_RX, + GPIO_GFN_CANFD1_TX, + GPIO_GFN_CANFD0_RX_A, + GPIO_GFN_CANFD0_TX_A, + GPIO_GFN_AVB0_AVTP_CAPTURE, + GPIO_GFN_AVB0_AVTP_MATCH, + GPIO_FN_AVB0_LINK, + GPIO_FN_AVB0_PHY_INT, + GPIO_FN_AVB0_MAGIC, + GPIO_FN_AVB0_MDC, + GPIO_FN_AVB0_MDIO, + GPIO_FN_AVB0_TXCREFCLK, + GPIO_FN_AVB0_TD3, + GPIO_FN_AVB0_TD2, + GPIO_FN_AVB0_TD1, + GPIO_FN_AVB0_TD0, + GPIO_FN_AVB0_TXC, + GPIO_FN_AVB0_TX_CTL, + GPIO_FN_AVB0_RD3, + GPIO_FN_AVB0_RD2, + GPIO_FN_AVB0_RD1, + GPIO_FN_AVB0_RD0, + GPIO_FN_AVB0_RXC, + GPIO_FN_AVB0_RX_CTL, + GPIO_GFN_IRQ0, + + /* GPSR2 */ + GPIO_GFN_FSO_TOE_N, + GPIO_GFN_FSO_CFE_1_N, + GPIO_GFN_FSO_CFE_0_N, + GPIO_GFN_SDA3, + GPIO_GFN_SCL3, + GPIO_GFN_MSIOF0_SS2, + GPIO_GFN_MSIOF0_SS1, + GPIO_GFN_MSIOF0_SYNC, + GPIO_GFN_MSIOF0_SCK, + GPIO_GFN_MSIOF0_TXD, + GPIO_GFN_MSIOF0_RXD, + GPIO_GFN_IRQ5, + GPIO_GFN_IRQ4, + GPIO_GFN_VI0_FIELD, + GPIO_GFN_VI0_DATA11, + GPIO_GFN_VI0_DATA10, + GPIO_GFN_VI0_DATA9, + GPIO_GFN_VI0_DATA8, + GPIO_GFN_VI0_DATA7, + GPIO_GFN_VI0_DATA6, + GPIO_GFN_VI0_DATA5, + GPIO_GFN_VI0_DATA4, + GPIO_GFN_VI0_DATA3, + GPIO_GFN_VI0_DATA2, + GPIO_GFN_VI0_DATA1, + GPIO_GFN_VI0_DATA0, + GPIO_GFN_VI0_VSYNC_N, + GPIO_GFN_VI0_HSYNC_N, + GPIO_GFN_VI0_CLKENB, + GPIO_GFN_VI0_CLK, + + /* GPSR3 */ + GPIO_GFN_VI1_FIELD, + GPIO_GFN_VI1_DATA11, + GPIO_GFN_VI1_DATA10, + GPIO_GFN_VI1_DATA9, + GPIO_GFN_VI1_DATA8, + GPIO_GFN_VI1_DATA7, + GPIO_GFN_VI1_DATA6, + GPIO_GFN_VI1_DATA5, + GPIO_GFN_VI1_DATA4, + GPIO_GFN_VI1_DATA3, + GPIO_GFN_VI1_DATA2, + GPIO_GFN_VI1_DATA1, + GPIO_GFN_VI1_DATA0, + GPIO_GFN_VI1_VSYNC_N, + GPIO_GFN_VI1_HSYNC_N, + GPIO_GFN_VI1_CLKENB, + GPIO_GFN_VI1_CLK, + + /* GPSR4 */ + GPIO_FN_GETHER_LINK_A, + GPIO_FN_GETHER_PHY_INT_A, + GPIO_FN_GETHER_MAGIC, + GPIO_FN_GETHER_MDC_A, + GPIO_FN_GETHER_MDIO_A, + GPIO_FN_GETHER_TXCREFCLK_MEGA, + GPIO_FN_GETHER_TXCREFCLK, + GPIO_FN_GETHER_TD3, + GPIO_FN_GETHER_TD2, + GPIO_FN_GETHER_TD1, + GPIO_FN_GETHER_TD0, + GPIO_FN_GETHER_TXC, + GPIO_FN_GETHER_TX_CTL, + GPIO_FN_GETHER_RD3, + GPIO_FN_GETHER_RD2, + GPIO_FN_GETHER_RD1, + GPIO_FN_GETHER_RD0, + GPIO_FN_GETHER_RXC, + GPIO_FN_GETHER_RX_CTL, + GPIO_GFN_SDA2, + GPIO_GFN_SCL2, + GPIO_GFN_SDA1, + GPIO_GFN_SCL1, + GPIO_GFN_SDA0, + GPIO_GFN_SCL0, + + /* GPSR5 */ + GPIO_FN_RPC_INT_N, + GPIO_FN_RPC_WP_N, + GPIO_FN_RPC_RESET_N, + GPIO_FN_QSPI1_SSL, + GPIO_FN_QSPI1_IO3, + GPIO_FN_QSPI1_IO2, + GPIO_FN_QSPI1_MISO_IO1, + GPIO_FN_QSPI1_MOSI_IO0, + GPIO_FN_QSPI1_SPCLK, + GPIO_FN_QSPI0_SSL, + GPIO_FN_QSPI0_IO3, + GPIO_FN_QSPI0_IO2, + GPIO_FN_QSPI0_MISO_IO1, + GPIO_FN_QSPI0_MOSI_IO0, + GPIO_FN_QSPI0_SPCLK, + + /* IPSR0 */ + GPIO_IFN_DU_DR2, + GPIO_FN_SCK4, + GPIO_FN_GETHER_RMII_CRS_DV, + GPIO_FN_A0, + GPIO_IFN_DU_DR3, + GPIO_FN_RX4, + GPIO_FN_GETHER_RMII_RX_ER, + GPIO_FN_A1, + GPIO_IFN_DU_DR4, + GPIO_FN_TX4, + GPIO_FN_GETHER_RMII_RXD0, + GPIO_FN_A2, + GPIO_IFN_DU_DR5, + GPIO_FN_CTS4_N, + GPIO_FN_GETHER_RMII_RXD1, + GPIO_FN_A3, + GPIO_IFN_DU_DR6, + GPIO_FN_RTS4_N_TANS, + GPIO_FN_GETHER_RMII_TXD_EN, + GPIO_FN_A4, + GPIO_IFN_DU_DR7, + GPIO_FN_GETHER_RMII_TXD0, + GPIO_FN_A5, + GPIO_IFN_DU_DG2, + GPIO_FN_GETHER_RMII_TXD1, + GPIO_FN_A6, + GPIO_IFN_DU_DG3, + GPIO_FN_CPG_CPCKOUT, + GPIO_FN_GETHER_RMII_REFCLK, + GPIO_FN_A7, + GPIO_FN_PWMFSW0, + + /* IPSR1 */ + GPIO_IFN_DU_DG4, + GPIO_FN_SCL5, + GPIO_FN_A8, + GPIO_IFN_DU_DG5, + GPIO_FN_SDA5, + GPIO_FN_GETHER_MDC_B, + GPIO_FN_A9, + GPIO_IFN_DU_DG6, + GPIO_FN_SCIF_CLK_A, + GPIO_FN_GETHER_MDIO_B, + GPIO_FN_A10, + GPIO_IFN_DU_DG7, + GPIO_FN_HRX0_A, + GPIO_FN_A11, + GPIO_IFN_DU_DB2, + GPIO_FN_HSCK0_A, + GPIO_FN_A12, + GPIO_FN_IRQ1, + GPIO_IFN_DU_DB3, + GPIO_FN_HRTS0_N_A, + GPIO_FN_A13, + GPIO_FN_IRQ2, + GPIO_IFN_DU_DB4, + GPIO_FN_HCTS0_N_A, + GPIO_FN_A14, + GPIO_FN_IRQ3, + GPIO_IFN_DU_DB5, + GPIO_FN_HTX0_A, + GPIO_FN_PWM0_A, + GPIO_FN_A15, + + /* IPSR2 */ + GPIO_IFN_DU_DB6, + GPIO_FN_MSIOF3_RXD, + GPIO_FN_A16, + GPIO_IFN_DU_DB7, + GPIO_FN_MSIOF3_TXD, + GPIO_FN_A17, + GPIO_IFN_DU_DOTCLKOUT, + GPIO_FN_MSIOF3_SS1, + GPIO_FN_GETHER_LINK_B, + GPIO_FN_A18, + GPIO_IFN_DU_EXHSYNC_DU_HSYNC, + GPIO_FN_MSIOF3_SS2, + GPIO_FN_GETHER_PHY_INT_B, + GPIO_FN_A19, + GPIO_FN_FXR_TXENA_N, + GPIO_IFN_DU_EXVSYNC_DU_VSYNC, + GPIO_FN_MSIOF3_SCK, + GPIO_FN_FXR_TXENB_N, + GPIO_IFN_DU_EXODDF_DU_ODDF_DISP_CDE, + GPIO_FN_MSIOF3_SYNC, + GPIO_IFN_IRQ0, + GPIO_FN_CC5_OSCOUT, + GPIO_IFN_VI0_CLK, + GPIO_FN_MSIOF2_SCK, + GPIO_FN_SCK3, + GPIO_FN_HSCK3, + + /* IPSR3 */ + GPIO_IFN_VI0_CLKENB, + GPIO_FN_MSIOF2_RXD, + GPIO_FN_RX3, + GPIO_FN_RD_WR_N, + GPIO_FN_HCTS3_N, + GPIO_IFN_VI0_HSYNC_N, + GPIO_FN_MSIOF2_TXD, + GPIO_FN_TX3, + GPIO_FN_HRTS3_N, + GPIO_IFN_VI0_VSYNC_N, + GPIO_FN_MSIOF2_SYNC, + GPIO_FN_CTS3_N, + GPIO_FN_HTX3, + GPIO_IFN_VI0_DATA0, + GPIO_FN_MSIOF2_SS1, + GPIO_FN_RTS3_N_TANS, + GPIO_FN_HRX3, + GPIO_IFN_VI0_DATA1, + GPIO_FN_MSIOF2_SS2, + GPIO_FN_SCK1, + GPIO_FN_SPEEDIN_A, + GPIO_IFN_VI0_DATA2, + GPIO_FN_AVB0_AVTP_PPS, + GPIO_IFN_VI0_DATA3, + GPIO_FN_HSCK1, + GPIO_IFN_VI0_DATA4, + GPIO_FN_HRTS1_N, + GPIO_FN_RX1_A, + + /* IPSR4 */ + GPIO_IFN_VI0_DATA5, + GPIO_FN_HCTS1_N, + GPIO_FN_TX1_A, + GPIO_IFN_VI0_DATA6, + GPIO_FN_HTX1, + GPIO_FN_CTS1_N, + GPIO_IFN_VI0_DATA7, + GPIO_FN_HRX1, + GPIO_FN_RTS1_N_TANS, + GPIO_IFN_VI0_DATA8, + GPIO_FN_HSCK2, + GPIO_IFN_VI0_DATA9, + GPIO_FN_HCTS2_N, + GPIO_FN_PWM1_A, + GPIO_FN_FSO_CFE_0_N_B, + GPIO_IFN_VI0_DATA10, + GPIO_FN_HRTS2_N, + GPIO_FN_PWM2_A, + GPIO_IFN_VI0_DATA11, + GPIO_FN_HTX2, + GPIO_FN_PWM3_A, + GPIO_IFN_VI0_FIELD, + GPIO_FN_HRX2, + GPIO_FN_PWM4_A, + GPIO_FN_CS1_N, + GPIO_FN_FSCLKST2_N_A, + + /* IPSR5 */ + GPIO_IFN_VI1_CLK, + GPIO_FN_MSIOF1_RXD, + GPIO_FN_CS0_N, + GPIO_IFN_VI1_CLKENB, + GPIO_FN_MSIOF1_TXD, + GPIO_FN_D0, + GPIO_IFN_VI1_HSYNC_N, + GPIO_FN_MSIOF1_SCK, + GPIO_FN_D1, + GPIO_IFN_VI1_VSYNC_N, + GPIO_FN_MSIOF1_SYNC, + GPIO_FN_D2, + GPIO_IFN_VI1_DATA0, + GPIO_FN_MSIOF1_SS1, + GPIO_FN_D3, + GPIO_FN_MMC_WP, + GPIO_IFN_VI1_DATA1, + GPIO_FN_MSIOF1_SS2, + GPIO_FN_D4, + GPIO_FN_MMC_CD, + GPIO_IFN_VI1_DATA2, + GPIO_FN_CANFD0_TX_B, + GPIO_FN_D5, + GPIO_FN_MMC_DS, + GPIO_IFN_VI1_DATA3, + GPIO_FN_CANFD0_RX_B, + GPIO_FN_D6, + GPIO_FN_MMC_CMD, + + /* IPSR6 */ + GPIO_IFN_VI1_DATA4, + GPIO_FN_CANFD_CLK_B, + GPIO_FN_D7, + GPIO_FN_MMC_D0, + GPIO_IFN_VI1_DATA5, + GPIO_FN_D8, + GPIO_FN_MMC_D1, + GPIO_IFN_VI1_DATA6, + GPIO_FN_D9, + GPIO_FN_MMC_D2, + GPIO_IFN_VI1_DATA7, + GPIO_FN_D10, + GPIO_FN_MMC_D3, + GPIO_IFN_VI1_DATA8, + GPIO_FN_D11, + GPIO_FN_MMC_CLK, + GPIO_IFN_VI1_DATA9, + GPIO_FN_TCLK1_A, + GPIO_FN_D12, + GPIO_FN_MMC_D4, + GPIO_IFN_VI1_DATA10, + GPIO_FN_TCLK2_A, + GPIO_FN_D13, + GPIO_FN_MMC_D5, + GPIO_IFN_VI1_DATA11, + GPIO_FN_SCL4, + GPIO_FN_D14, + GPIO_FN_MMC_D6, + + /* IPSR7 */ + GPIO_IFN_VI1_FIELD, + GPIO_FN_SDA4, + GPIO_FN_D15, + GPIO_FN_MMC_D7, + GPIO_IFN_SCL0, + GPIO_FN_CLKOUT, + GPIO_IFN_SDA0, + GPIO_FN_BS_N, + GPIO_FN_SCK0, + GPIO_FN_HSCK0_B, + GPIO_IFN_SCL1, + GPIO_FN_TPU0TO2, + GPIO_FN_RD_N, + GPIO_FN_CTS0_N, + GPIO_FN_HCTS0_N_B, + GPIO_IFN_SDA1, + GPIO_FN_TPU0TO3, + GPIO_FN_WE0_N, + GPIO_FN_RTS0_N_TANS, + GPIO_FN_HRTS0_N_B, + GPIO_IFN_SCL2, + GPIO_FN_WE1_N, + GPIO_FN_RX0, + GPIO_FN_HRX0_B, + GPIO_IFN_SDA2, + GPIO_FN_EX_WAIT0, + GPIO_FN_TX0, + GPIO_FN_HTX0_B, + GPIO_IFN_AVB0_AVTP_MATCH, + GPIO_FN_TPU0TO0, + + /* IPSR8 */ + GPIO_IFN_AVB0_AVTP_CAPTURE, + GPIO_FN_TPU0TO1, + GPIO_IFN_CANFD0_TX_A, + GPIO_FN_FXR_TXDA, + GPIO_FN_PWM0_B, + GPIO_FN_DU_DISP, + GPIO_IFN_CANFD0_RX_A, + GPIO_FN_RXDA_EXTFXR, + GPIO_FN_PWM1_B, + GPIO_FN_DU_CDE, + GPIO_IFN_CANFD1_TX, + GPIO_FN_FXR_TXDB, + GPIO_FN_PWM2_B, + GPIO_FN_TCLK1_B, + GPIO_FN_TX1_B, + GPIO_IFN_CANFD1_RX, + GPIO_FN_RXDB_EXTFXR, + GPIO_FN_PWM3_B, + GPIO_FN_TCLK2_B, + GPIO_FN_RX1_B, + GPIO_IFN_CANFD_CLK_A, + GPIO_FN_CLK_EXTFXR, + GPIO_FN_PWM4_B, + GPIO_FN_SPEEDIN_B, + GPIO_FN_SCIF_CLK_B, + GPIO_IFN_DIGRF_CLKIN, + GPIO_FN_DIGRF_CLKEN_IN, + GPIO_IFN_DIGRF_CLKOUT, + GPIO_FN_DIGRF_CLKEN_OUT, + + /* IPSR9 */ + GPIO_IFN_IRQ4, + GPIO_FN_VI0_DATA12, + GPIO_IFN_IRQ5, + GPIO_FN_VI0_DATA13, + GPIO_IFN_MSIOF0_RXD, + GPIO_FN_DU_DR0, + GPIO_FN_VI0_DATA14, + GPIO_IFN_MSIOF0_TXD, + GPIO_FN_DU_DR1, + GPIO_FN_VI0_DATA15, + GPIO_IFN_MSIOF0_SCK, + GPIO_FN_DU_DG0, + GPIO_FN_VI0_DATA16, + GPIO_IFN_MSIOF0_SYNC, + GPIO_FN_DU_DG1, + GPIO_FN_VI0_DATA17, + GPIO_IFN_MSIOF0_SS1, + GPIO_FN_DU_DB0, + GPIO_FN_TCLK3, + GPIO_FN_VI0_DATA18, + GPIO_IFN_MSIOF0_SS2, + GPIO_FN_DU_DB1, + GPIO_FN_TCLK4, + GPIO_FN_VI0_DATA19, + + /* IPSR10 */ + GPIO_IFN_SCL3, + GPIO_FN_VI0_DATA20, + GPIO_IFN_SDA3, + GPIO_FN_VI0_DATA21, + GPIO_IFN_FSO_CFE_0_N, + GPIO_FN_VI0_DATA22, + GPIO_IFN_FSO_CFE_1_N, + GPIO_FN_VI0_DATA23, + GPIO_IFN_FSO_TOE_N, +}; + +#endif /* __ASM_R8A7798_GPIO_H__ */ diff --git a/arch/arm/include/asm/arch-rcar_gen3/r8a7798.h b/arch/arm/include/asm/arch-rcar_gen3/r8a7798.h new file mode 100644 index 0000000..06514f0 --- /dev/null +++ b/arch/arm/include/asm/arch-rcar_gen3/r8a7798.h @@ -0,0 +1,34 @@ +/* + * arch/arm/include/asm/arch-rcar_gen3/r8a7798.h + * This file defines registers and value for r8a7798. + * + * Copyright (C) 2018 Renesas Electronics Corp. + * Copyright (C) 2018 Cogent Embedded, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __ASM_ARCH_R8A7798_H +#define __ASM_ARCH_R8A7798_H + +#include "rcar-base.h" + +/* Module stop control/status register bits */ +#define MSTP0_BITS 0x00230000 +#define MSTP1_BITS 0xFFFFFFFF +#define MSTP2_BITS 0x14062FD8 +#define MSTP3_BITS 0xFFFFFFDF +#define MSTP4_BITS 0x80000184 +#define MSTP5_BITS 0x83FFFFFF +#define MSTP6_BITS 0xFFFFFFFF +#define MSTP7_BITS 0xFFFFFFFF +#define MSTP8_BITS 0x7FF3FFF4 +#define MSTP9_BITS 0xFBF7FF97 +#define MSTP10_BITS 0xFFFEFFE0 +#define MSTP11_BITS 0x000000B7 + +/* SDHI */ +#define CONFIG_SYS_SH_SDHI2_BASE 0xEE140000 /* either MMC0 */ +#define CONFIG_SYS_SH_SDHI_NR_CHANNEL 1 + +#endif /* __ASM_ARCH_R8A7798_H */ diff --git a/arch/arm/include/asm/arch-rcar_gen3/rcar_gen3.h b/arch/arm/include/asm/arch-rcar_gen3/rcar_gen3.h index c2ba0fb..c3568b0 100644 --- a/arch/arm/include/asm/arch-rcar_gen3/rcar_gen3.h +++ b/arch/arm/include/asm/arch-rcar_gen3/rcar_gen3.h @@ -16,6 +16,8 @@ #include #elif defined(CONFIG_R8A7797) #include + #elif defined(CONFIG_R8A7798) + #include #else #error "SOC Name not defined" #endif diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c index 4b9a61b..95129ce 100644 --- a/drivers/mtd/spi/sf_probe.c +++ b/drivers/mtd/spi/sf_probe.c @@ -383,7 +383,7 @@ int spi_flash_probe_slave(struct spi_slave *spi, struct spi_flash *flash) puts("\n"); #endif #ifndef CONFIG_SPI_FLASH_BAR -#ifndef CONFIG_R8A7797 +#if !defined(CONFIG_R8A7797) && !defined(CONFIG_R8A7798) if (((flash->dual_flash == SF_SINGLE_FLASH) && (flash->size > SPI_FLASH_16MB_BOUN)) || ((flash->dual_flash > SF_SINGLE_FLASH) && diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig index 1a26543..b19ece1 100644 --- a/drivers/net/Kconfig +++ b/drivers/net/Kconfig @@ -2,7 +2,7 @@ menu "Network Device Support" config RAVB_1000BASE bool "Renesas Ethernet AVB support 1000Base" - default y if R8A7795 || R8A7796X || R8A7797 + default y if R8A7795 || R8A7796X || R8A7797 || R8A7798 depends on RCAR_GEN3 endmenu diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index 4bf493e..8226591 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -380,8 +380,12 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd) struct phy_device *phy; /* Configure e-dmac registers */ + val = EMDR_DESC | EDMR_EL; +#if defined(CONFIG_R8A7798) + val |= EDMR_NBST; +#endif sh_eth_write(eth, (sh_eth_read(eth, EDMR) & ~EMDR_DESC_R) | - (EMDR_DESC | EDMR_EL), EDMR); + val, EDMR); sh_eth_write(eth, 0, EESIPR); sh_eth_write(eth, 0, TRSCER); @@ -417,7 +421,8 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd) #if defined(CONFIG_CPU_SH7734) || defined(CONFIG_R8A7740) sh_eth_write(eth, CONFIG_SH_ETHER_SH7734_MII, RMII_MII); #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ - defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) + defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) || \ + defined(CONFIG_R8A7798) sh_eth_write(eth, sh_eth_read(eth, RMIIMR) | 0x1, RMIIMR); #endif /* Configure phy */ @@ -444,7 +449,7 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd) sh_eth_write(eth, 1, RTRATE); #elif defined(CONFIG_CPU_SH7724) || defined(CONFIG_R8A7790) || \ defined(CONFIG_R8A7791) || defined(CONFIG_R8A7793) || \ - defined(CONFIG_R8A7794) + defined(CONFIG_R8A7794) || defined(CONFIG_R8A7798) val = ECMR_RTM; #endif } else if (phy->speed == 10) { diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h index 5cb520c..3c30d42 100644 --- a/drivers/net/sh_eth.h +++ b/drivers/net/sh_eth.h @@ -361,6 +361,9 @@ static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = { #elif defined(CONFIG_R7S72100) #define SH_ETH_TYPE_RZ #define BASE_IO_ADDR 0xE8203000 +#elif defined(CONFIG_R8A7798) +#define SH_ETH_TYPE_GETHER +#define BASE_IO_ADDR 0xE7400000 #endif /* @@ -377,6 +380,7 @@ enum EDSR_BIT { /* EDMR */ enum DMAC_M_BIT { + EDMR_NBST = 0x80, /* DMA transfer burst mode */ EDMR_DL1 = 0x20, EDMR_DL0 = 0x10, #if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ) EDMR_SRST = 0x03, /* Receive/Send reset */ @@ -567,7 +571,8 @@ enum FELIC_MODE_BIT { #ifdef CONFIG_CPU_SH7724 ECMR_RTM = 0x00000010, #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ - defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) + defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) || \ + defined(CONFIG_R8A7798) ECMR_RTM = 0x00000004, #endif diff --git a/drivers/serial/serial_sh.h b/drivers/serial/serial_sh.h index 478824e..ded0d3d 100644 --- a/drivers/serial/serial_sh.h +++ b/drivers/serial/serial_sh.h @@ -227,7 +227,7 @@ struct uart_port { #elif defined(CONFIG_R8A7790) || defined(CONFIG_R8A7791) || \ defined(CONFIG_R8A7793) || defined(CONFIG_R8A7794) || \ defined(CONFIG_R8A7795) || defined(CONFIG_R8A7796X) || \ - defined(CONFIG_R8A7797) + defined(CONFIG_R8A7797) || defined(CONFIG_R8A7798) # define SCIF_ORER 0x0001 # define SCSCR_INIT(port) (port->clk_mode == EXT_CLK ? 0x32 : 0x30) /* TIE=0,RIE=0,TE=1,RE=1,REIE=0, */ diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h index dc5560d..a3721ad 100644 --- a/include/configs/rcar-gen3-common.h +++ b/include/configs/rcar-gen3-common.h @@ -134,6 +134,12 @@ #endif #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_1_SIZE +#elif defined(CONFIG_R8A7798) +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 (0x40000000 + DRAM_RSV_SIZE) /* legacy */ +#define PHYS_SDRAM_1_SIZE ((unsigned long)(0x80000000 - DRAM_RSV_SIZE)) +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_1_SIZE #else #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_SYS_SDRAM_BASE 0x40000000 -- 1.9.1