    8    (            +D \                                                      '   ti,dra7-evm ti,dra742 ti,dra74 ti,dra7           &         
   7TI DRA742      tc358768_refclk         A          1-          fixed-clock         W          backlight           A          *j                *Q         $  *?                                    *:           led-backlight  =      chosen           =/ocp/serial@4806a000          aliases         *1/connector 0         I/ocp/i2c@48070000            N/ocp/i2c@48072000            S/ocp/i2c@48060000            X/ocp/i2c@4807a000            ]/ocp/i2c@4807c000            b/ocp/serial@4806a000             j/ocp/serial@4806c000             r/ocp/serial@48020000             z/ocp/serial@4806e000             /ocp/serial@48066000             /ocp/serial@48068000             /ocp/serial@48420000             /ocp/serial@48422000             /ocp/serial@48424000             /ocp/serial@4ae2b000          &   /ocp/ethernet@48484000/slave@48480200         &   /ocp/ethernet@48484000/slave@48480300            /ocp/can@4ae3c000            /ocp/can@48480000            /ocp/qspi@4b300000           /ocp/ipu@58820000            /ocp/ipu@55020000            /ocp/dsp@40800000            /ocp/dsp@41000000         	   /display r@1         /sound0       #  /ocp/dss@58000000/encoder@58060000        timer            arm,armv7-timer       0                                
           &         interrupt-controller@48211000            arm,cortex-a15-gic                   ,         @  =    H!            H!              H!@             H!`                       	           &           A         interrupt-controller@48281000         &   ti,omap5-wugen-mpu ti,omap4-wugen-mpu                    ,           =    H(                 &           A         cpus                                 cpu@0           Icpu          arm,cortex-a15          =            U           i           pcpu         |                                          A         cpu@1           Icpu          arm,cortex-a15          =           U           i           pcpu         |                                opp-table            operating-points-v2-ti-cpu                              A      opp_nom-1000000000              ;          , P 0 , P 0                             opp_od-1176000000               FV          @  @ @  @                    opp_high@1500000000             Yh/          v ~  v ~                        soc          ti,omap-infra      mpu          ti,omap5-mpu            mpu          ocp          ti,dra7-l3-noc simple-bus                                                           l3_main_1 l3_main_2          =    D              E                                          
      l4@4a000000          ti,dra7-l4-cfg simple-bus                                        J    "         A     scm@2000             ti,dra7-scm-core simple-bus         =                                                             A     scm_conf@0           syscon simple-bus           =                                                           A   	   pbias_regulator@e00          ti,pbias-dra7 ti,pbias-omap         =                 	        A     pbias_mmc_omap5         pbias_mmc_omap5         ' w@        ? 2Z        A            clocks                                    A     dss_deshdcp_clk@558         W             ti,gate-clock           i   
        d            =  X        A        ehrpwm0_tbclk@558           W             ti,gate-clock           i           d           =  X        A         ehrpwm1_tbclk@558           W             ti,gate-clock           i           d           =  X        A         ehrpwm2_tbclk@558           W             ti,gate-clock           i           d           =  X        A         sys_32k_ck          W             ti,mux-clock            i                    d           =          A   P            pinmux@1400          ti,dra7-padconf pinctrl-single          =     h                                  q           ,                                ?        A      mmc1_pins_default         0    T     X     \     `     d     h           A         mmc1_pins_sdr12       0    T     X     \     `     d     h           A         mmc1_pins_hs          0    T   X   \   `   d   h         A         mmc1_pins_sdr25       0    T   X   \   `   d   h         A         mmc1_pins_sdr50       0    T   X   \   `   d   h         A         mmc1_pins_ddr50       0    T    X    \    `    d    h          A         mmc1_pins_sdr104          0    T    X    \    `    d    h          A         mmc2_pins_default         P                                                            A         mmc2_pins_hs          P                                                            A         mmc2_pins_ddr_3_3v_rev11          P                                                  A        mmc2_pins_ddr_1_8v_rev11          P                                                  A         mmc2_pins_ddr_rev20       P                                                            A         mmc2_pins_hs200       P                                                  A         mmc4_pins_default         0                            A         mmc4_pins_hs          0                            A         mmc3_pins_default         0    |                                    A        mmc3_pins_hs          0    |                                    A        mmc3_pins_sdr12       0    |                                    A        mmc3_pins_sdr25       0    |                                    A        mmc3_pins_sdr50       0    |                              A        mmc4_pins_sdr12       0                            A         mmc4_pins_sdr25       0                            A         dcan1_pins_default                           A         dcan1_pins_sleep                            A         pinmux_mcasp8_axr2_pin                      A         pinmux_hdmi_i2c_pins_default                              A  	      pinmux_hdmi_i2c_pins_ddc                            A  
      dcan2_pins_default                          A         dcan2_pins_sleep                            A            scm_conf@1c04            syscon          =                         A         scm_conf@1c24            syscon          =  $   $        A         dma-router@b78           ti,dra7-dma-crossbar            =  x                                                        A         dma-router@c78           ti,dra7-dma-crossbar            =  x   |                                                     A            cm_core_aon@5000             ti,dra7-cm-core-aon simple-bus                                   =  P                   P             A     clocks                                    A     atl_clkin0_ck           W             ti,dra7-atl-clock           i                  A         atl_clkin1_ck           W             ti,dra7-atl-clock           i                  A         atl_clkin2_ck           W             ti,dra7-atl-clock           i                  A         atl_clkin3_ck           W             ti,dra7-atl-clock           i                  A         hdmi_clkin_ck           W             fixed-clock                     A   0      mlb_clkin_ck            W             fixed-clock                     A         mlbp_clkin_ck           W             fixed-clock                     A         pciesref_acs_clk_ck         W             fixed-clock                  A   @      ref_clkin0_ck           W             fixed-clock                     A        ref_clkin1_ck           W             fixed-clock                     A        ref_clkin2_ck           W             fixed-clock                     A        ref_clkin3_ck           W             fixed-clock                     A        rmii_clk_ck         W             fixed-clock                     A         sdvenc_clkin_ck         W             fixed-clock                     A  !      secure_32k_clk_src_ck           W             fixed-clock                    A   k      sys_clk32_crystal_ck            W             fixed-clock                    A         sys_clk32_pseudo_ck         W             fixed-factor-clock          i           !           ,  b        A         virt_12000000_ck            W             fixed-clock                   A   Y      virt_13000000_ck            W             fixed-clock          ]@        A  "      virt_16800000_ck            W             fixed-clock          Y         A   [      virt_19200000_ck            W             fixed-clock         $         A   \      virt_20000000_ck            W             fixed-clock         1-         A   Z      virt_26000000_ck            W             fixed-clock                 A   ]      virt_27000000_ck            W             fixed-clock                 A   ^      virt_38400000_ck            W             fixed-clock         I         A   _      sys_clkin2          W             fixed-clock         X         A   `      usb_otg_clkin_ck            W             fixed-clock                     A   h      video1_clkin_ck         W             fixed-clock                     A   :      video1_m2_clkin_ck          W             fixed-clock                     A   /      video2_clkin_ck         W             fixed-clock                     A   ;      video2_m2_clkin_ck          W             fixed-clock                     A   .      dpll_abe_ck@1e0         W             ti,omap4-dpll-m4xen-clock           i              =                A         dpll_abe_x2_ck          W             ti,omap4-dpll-x2-clock          i           A         dpll_abe_m2x2_ck@1f0            W             ti,divider-clock            i           6           A           =           S         j        A         abe_clk@108         W             ti,divider-clock            i           6           =                   A   b      dpll_abe_m2_ck@1f0          W             ti,divider-clock            i           6           A           =           S         j        A   d      dpll_abe_m3x2_ck@1f4            W             ti,divider-clock            i           6           A           =           S         j        A         dpll_core_byp_mux@12c           W             ti,mux-clock            i              d           =  ,        A         dpll_core_ck@120            W             ti,omap4-dpll-core-clock            i              =     $  ,  (        A         dpll_core_x2_ck         W             ti,omap4-dpll-x2-clock          i           A         dpll_core_h12x2_ck@13c          W             ti,divider-clock            i           6   ?        A           =  <         S         j        A         mpu_dpll_hs_clk_div         W             fixed-factor-clock          i           !           ,           A         dpll_mpu_ck@160         W             ti,omap5-mpu-dpll-clock         i              =  `  d  l  h        A         dpll_mpu_m2_ck@170          W             ti,divider-clock            i           6           A           =  p         S         j        A         mpu_dclk_div            W             fixed-factor-clock          i           !           ,           A   o      dsp_dpll_hs_clk_div         W             fixed-factor-clock          i           !           ,           A         dpll_dsp_byp_mux@240            W             ti,mux-clock            i              d           =  @        A         dpll_dsp_ck@234         W             ti,omap4-dpll-clock         i              =  4  8  @  <                    #F         A          dpll_dsp_m2_ck@244          W             ti,divider-clock            i            6           A           =  D         S         j           !        #F         A   !      iva_dpll_hs_clk_div         W             fixed-factor-clock          i           !           ,           A   "      dpll_iva_byp_mux@1ac            W             ti,mux-clock            i      "        d           =          A   #      dpll_iva_ck@1a0         W             ti,omap4-dpll-clock         i      #        =                   $        Ep}@        A   $      dpll_iva_m2_ck@1b0          W             ti,divider-clock            i   $        6           A           =           S         j           %        %        A   %      iva_dclk            W             fixed-factor-clock          i   %        !           ,           A   q      dpll_gpu_byp_mux@2e4            W             ti,mux-clock            i              d           =          A   &      dpll_gpu_ck@2d8         W             ti,omap4-dpll-clock         i      &        =                   '        Ly@        A   '      dpll_gpu_m2_ck@2e8          W             ti,divider-clock            i   '        6           A           =           S         j           (        _(k        A   (      dpll_core_m2_ck@130         W             ti,divider-clock            i           6           A           =  0         S         j        A   )      core_dpll_out_dclk_div          W             fixed-factor-clock          i   )        !           ,           A   s      dpll_ddr_byp_mux@21c            W             ti,mux-clock            i              d           =          A   *      dpll_ddr_ck@210         W             ti,omap4-dpll-clock         i      *        =                A   +      dpll_ddr_m2_ck@220          W             ti,divider-clock            i   +        6           A           =            S         j        A   e      dpll_gmac_byp_mux@2b4           W             ti,mux-clock            i              d           =          A   ,      dpll_gmac_ck@2a8            W             ti,omap4-dpll-clock         i      ,        =                A   -      dpll_gmac_m2_ck@2b8         W             ti,divider-clock            i   -        6           A           =           S         j        A   f      video2_dclk_div         W             fixed-factor-clock          i   .        !           ,           A   u      video1_dclk_div         W             fixed-factor-clock          i   /        !           ,           A   v      hdmi_dclk_div           W             fixed-factor-clock          i   0        !           ,           A   w      per_dpll_hs_clk_div         W             fixed-factor-clock          i           !           ,           A   C      usb_dpll_hs_clk_div         W             fixed-factor-clock          i           !           ,           A   G      eve_dpll_hs_clk_div         W             fixed-factor-clock          i           !           ,           A   1      dpll_eve_byp_mux@290            W             ti,mux-clock            i      1        d           =          A   2      dpll_eve_ck@284         W             ti,omap4-dpll-clock         i      2        =                A   3      dpll_eve_m2_ck@294          W             ti,divider-clock            i   3        6           A           =           S         j        A   4      eve_dclk_div            W             fixed-factor-clock          i   4        !           ,           A         dpll_core_h13x2_ck@140          W             ti,divider-clock            i           6   ?        A           =  @         S         j        A  #      dpll_core_h14x2_ck@144          W             ti,divider-clock            i           6   ?        A           =  D         S         j        A   Q      dpll_core_h22x2_ck@154          W             ti,divider-clock            i           6   ?        A           =  T         S         j        A   =      dpll_core_h23x2_ck@158          W             ti,divider-clock            i           6   ?        A           =  X         S         j        A   V      dpll_core_h24x2_ck@15c          W             ti,divider-clock            i           6   ?        A           =  \         S         j        A  $      dpll_ddr_x2_ck          W             ti,omap4-dpll-x2-clock          i   +        A   5      dpll_ddr_h11x2_ck@228           W             ti,divider-clock            i   5        6   ?        A           =  (         S         j        A  %      dpll_dsp_x2_ck          W             ti,omap4-dpll-x2-clock          i            A   6      dpll_dsp_m3x2_ck@248            W             ti,divider-clock            i   6        6           A           =  H         S         j           7        ׄ         A   7      dpll_gmac_x2_ck         W             ti,omap4-dpll-x2-clock          i   -        A   8      dpll_gmac_h11x2_ck@2c0          W             ti,divider-clock            i   8        6   ?        A           =           S         j        A   9      dpll_gmac_h12x2_ck@2c4          W             ti,divider-clock            i   8        6   ?        A           =           S         j        A  &      dpll_gmac_h13x2_ck@2c8          W             ti,divider-clock            i   8        6   ?        A           =           S         j        A         dpll_gmac_m3x2_ck@2bc           W             ti,divider-clock            i   8        6           A           =           S         j        A  '      gmii_m_clk_div          W             fixed-factor-clock          i   9        !           ,           A  (      hdmi_clk2_div           W             fixed-factor-clock          i   0        !           ,           A  )      hdmi_div_clk            W             fixed-factor-clock          i   0        !           ,           A  *      l3_iclk_div@100         W             ti,divider-clock            6           d           =           i                    A   
      l4_root_clk_div         W             fixed-factor-clock          i   
        !           ,           A         video1_clk2_div         W             fixed-factor-clock          i   :        !           ,           A  +      video1_div_clk          W             fixed-factor-clock          i   :        !           ,           A  ,      video2_clk2_div         W             fixed-factor-clock          i   ;        !           ,           A  -      video2_div_clk          W             fixed-factor-clock          i   ;        !           ,           A  .      dummy_ck            W             fixed-clock                     A  /         clockdomains            A  0      mpu_cm@300           ti,omap4-cm         =                                                         A  1   clk@20           ti,clkctrl          =               W           A  2         dsp1_cm@400          ti,omap4-cm         =                                                         A  3   clk@20           ti,clkctrl          =               W           A  4         ipu1_cm@500          ti,omap4-cm         =      @                                                   A  5   clk@20           ti,clkctrl          =                W              <                  =        A   <         ipu_cm@540           ti,omap4-cm         =  @                                          @           A  6   clk@0            ti,clkctrl          =       D        W           A            dsp2_cm@600          ti,omap4-cm         =                                                         A  7   clk@20           ti,clkctrl          =               W           A  8         rtc_cm@700           ti,omap4-cm         =                                                         A  9   clk@40           ti,clkctrl          =   @           W           A  :            cm_core@8000             ti,dra7-cm-core simple-bus                                   =     0                  0         A  ;   clocks                                    A  <   dpll_pcie_ref_ck@200            W             ti,omap4-dpll-clock         i              =                 A   >      dpll_pcie_ref_m2ldo_ck@210          W             ti,divider-clock            i   >        6           A           =           S         j        A   ?      apll_pcie_in_clk_mux@4ae06118            ti,mux-clock            i   ?   @        W            =             d           A   A      apll_pcie_ck@21c            W             ti,dra7-apll-clock          i   A   >        =             A   B      optfclk_pciephy_div@4a00821c             ti,divider-clock            i   B        W            =                        d           6           A         apll_pcie_clkvcoldo         W             fixed-factor-clock          i   B        !           ,           A  =      apll_pcie_clkvcoldo_div         W             fixed-factor-clock          i   B        !           ,           A  >      apll_pcie_m2_ck         W             fixed-factor-clock          i   B        !           ,           A   j      dpll_per_byp_mux@14c            W             ti,mux-clock            i      C        d           =  L        A   D      dpll_per_ck@140         W             ti,omap4-dpll-clock         i      D        =  @  D  L  H        A   E      dpll_per_m2_ck@150          W             ti,divider-clock            i   E        6           A           =  P         S         j        A   F      func_96m_aon_dclk_div           W             fixed-factor-clock          i   F        !           ,           A   x      dpll_usb_byp_mux@18c            W             ti,mux-clock            i      G        d           =          A   H      dpll_usb_ck@180         W             ti,omap4-dpll-j-type-clock          i      H        =                A   I      dpll_usb_m2_ck@190          W             ti,divider-clock            i   I        6           A           =           S         j        A   M      dpll_pcie_ref_m2_ck@210         W             ti,divider-clock            i   >        6           A           =           S         j        A   i      dpll_per_x2_ck          W             ti,omap4-dpll-x2-clock          i   E        A   J      dpll_per_h11x2_ck@158           W             ti,divider-clock            i   J        6   ?        A           =  X         S         j        A   K      dpll_per_h12x2_ck@15c           W             ti,divider-clock            i   J        6   ?        A           =  \         S         j        A  ?      dpll_per_h13x2_ck@160           W             ti,divider-clock            i   J        6   ?        A           =  `         S         j        A  @      dpll_per_h14x2_ck@164           W             ti,divider-clock            i   J        6   ?        A           =  d         S         j        A   R      dpll_per_m2x2_ck@150            W             ti,divider-clock            i   J        6           A           =  P         S         j        A   L      dpll_usb_clkdcoldo          W             fixed-factor-clock          i   I        !           ,           A   O      func_128m_clk           W             fixed-factor-clock          i   K        !           ,           A  A      func_12m_fclk           W             fixed-factor-clock          i   L        !           ,           A  B      func_24m_clk            W             fixed-factor-clock          i   F        !           ,           A  C      func_48m_fclk           W             fixed-factor-clock          i   L        !           ,           A  D      func_96m_fclk           W             fixed-factor-clock          i   L        !           ,           A  E      l3init_60m_fclk@104         W             ti,divider-clock            i   M        =                        A  F      clkout2_clk@6b0         W             ti,gate-clock           i   N        d           =          A  G      l3init_960m_gfclk@6c0           W             ti,gate-clock           i   O        d           =          A  H      usb_phy1_always_on_clk32k@640           W             ti,gate-clock           i   P        d           =  @        A         usb_phy2_always_on_clk32k@688           W             ti,gate-clock           i   P        d           =          A         usb_phy3_always_on_clk32k@698           W             ti,gate-clock           i   P        d           =          A         gpu_core_gclk_mux@1220          W             ti,mux-clock            i   Q   R   (        d           =              S           (        A   S      gpu_hyd_gclk_mux@1220           W             ti,mux-clock            i   Q   R   (        d           =              T           (        A   T      l3instr_ts_gclk_div@e50         W             ti,divider-clock            i   U        d           =  P                          A  I      vip1_gclk_mux@1020          W             ti,mux-clock            i   
   V        d           =           A  J      vip2_gclk_mux@1028          W             ti,mux-clock            i   
   V        d           =  (        A  K      vip3_gclk_mux@1030          W             ti,mux-clock            i   
   V        d           =  0        A  L         clockdomains            A  M   coreaon_clkdm            ti,clockdomain          i   I        A  N         coreaon_cm@600           ti,omap4-cm         =                                                         A  O   clk@20           ti,clkctrl          =               W           A            l3main1_cm@700           ti,omap4-cm         =                                                         A  P   clk@20           ti,clkctrl          =       t        W           A  Q         ipu2_cm@900          ti,omap4-cm         =  	                                           	            A  R   clk@20           ti,clkctrl          =               W           A  S         dma_cm@a00           ti,omap4-cm         =  
                                           
            A  T   clk@20           ti,clkctrl          =               W           A  U         emif_cm@b00          ti,omap4-cm         =                                                         A  V   clk@20           ti,clkctrl          =               W           A  W         atl_cm@c00           ti,omap4-cm         =                                                         A  X   clk@0            ti,clkctrl          =               W           A            l4cfg_cm@d00             ti,omap4-cm         =                                                         A  Y   clk@20           ti,clkctrl          =               W           A  Z         l3instr_cm@e00           ti,omap4-cm         =                                                         A  [   clk@20           ti,clkctrl          =               W           A  \         dss_cm@1100          ti,omap4-cm         =                                                         A  ]   clk@20           ti,clkctrl          =               W           A            l3init_cm@1300           ti,omap4-cm         =                                                         A  ^   clk@20           ti,clkctrl          =               W           A            l4per_cm@1700            ti,omap4-cm         =                                                         A  _   clk@0            ti,clkctrl          =              W              W  h              X        A   W               l4@4ae00000          ti,dra7-l4-wkup simple-bus                                       J            A  `   counter@4000             ti,omap-counter32k          =  @    @        counter_32k         A  a      prm@6000             ti,dra7-prm simple-bus          =  `   0                                                          `   0         A  b   clocks                                    A  c   sys_clkin1@110          W             ti,mux-clock            i   Y   Z   [   \   ]   ^   _        =           S        A         abe_dpll_sys_clk_mux@118            W             ti,mux-clock            i      `        =          A   a      abe_dpll_bypass_clk_mux@114         W             ti,mux-clock            i   a   P        =          A         abe_dpll_clk_mux@10c            W             ti,mux-clock            i   a   P        =          A         abe_24m_fclk@11c            W             ti,divider-clock            i           =                        A   X      aess_fclk@178           W             ti,divider-clock            i   b        =  x        6           A   c      abe_giclk_div@174           W             ti,divider-clock            i   c        =  t        6           A  d      abe_lp_clk_div@1d8          W             ti,divider-clock            i           =                         A         abe_sys_clk_div@120         W             ti,divider-clock            i           =           6           A  e      adc_gfclk_mux@1dc           W             ti,mux-clock            i      `   P        =          A  f      sys_clk1_dclk_div@1c8           W             ti,divider-clock            i           6   @        =                   A   l      sys_clk2_dclk_div@1cc           W             ti,divider-clock            i   `        6   @        =                   A   m      per_abe_x1_dclk_div@1bc         W             ti,divider-clock            i   d        6   @        =                   A   n      dsp_gclk_div@18c            W             ti,divider-clock            i   !        6   @        =                   A   p      gpu_dclk@1a0            W             ti,divider-clock            i   (        6   @        =                   A   r      emif_phy_dclk_div@190           W             ti,divider-clock            i   e        6   @        =                   A   t      gmac_250m_dclk_div@19c          W             ti,divider-clock            i   f        6   @        =                   A   g      gmac_main_clk           W             fixed-factor-clock          i   g        !           ,           A         l3init_480m_dclk_div@1ac            W             ti,divider-clock            i   M        6   @        =                   A   y      usb_otg_dclk_div@184            W             ti,divider-clock            i   h        6   @        =                   A   z      sata_dclk_div@1c0           W             ti,divider-clock            i           6   @        =                   A   {      pcie2_dclk_div@1b8          W             ti,divider-clock            i   i        6   @        =                   A   |      pcie_dclk_div@1b4           W             ti,divider-clock            i   j        6   @        =                   A   }      emu_dclk_div@194            W             ti,divider-clock            i           6   @        =                   A   ~      secure_32k_dclk_div@1c4         W             ti,divider-clock            i   k        6   @        =                   A         clkoutmux0_clk_mux@158          W             ti,mux-clock          X  i   l   m   n   o   p   q   r   s   t   g   u   v   w   x   y   z   {   |   }   ~              =  X        A  g      clkoutmux1_clk_mux@15c          W             ti,mux-clock          X  i   l   m   n   o   p   q   r   s   t   g   u   v   w   x   y   z   {   |   }   ~              =  \        A  h      clkoutmux2_clk_mux@160          W             ti,mux-clock          X  i   l   m   n   o   p   q   r   s   t   g   u   v   w   x   y   z   {   |   }   ~              =  `        A   N      custefuse_sys_gfclk_div         W             fixed-factor-clock          i           !           ,           A  i      eve_clk@180         W             ti,mux-clock            i   4   7        =          A  j      hdmi_dpll_clk_mux@164           W             ti,mux-clock            i      `        =  d        A  k      mlb_clk@134         W             ti,divider-clock            i           6   @        =  4                 A  l      mlbp_clk@130            W             ti,divider-clock            i           6   @        =  0                 A  m      per_abe_x1_gfclk2_div@138           W             ti,divider-clock            i   d        6   @        =  8                 A  n      timer_sys_clk_div@144           W             ti,divider-clock            i           =  D        6           A  o      video1_dpll_clk_mux@168         W             ti,mux-clock            i      `        =  h        A  p      video2_dpll_clk_mux@16c         W             ti,mux-clock            i      `        =  l        A  q      wkupaon_iclk_mux@108            W             ti,mux-clock            i              =          A   U         clockdomains            A  r      wkupaon_cm@1800          ti,omap4-cm         =                                                         A  s   clk@20           ti,clkctrl          =       l        W           A               scm_conf@c000            syscon          =              A            axi@0            simple-bus                                   Q   Q     0               pcie@51000000           =Q       Q     L               rc_dbics ti_conf config                                                              Ipci       0               0                0  0                             ,                                  pcie1                    
  pcie-phy0                         0                     `  C                                                                                            Qokay             ti,dra746-pcie-rc ti,dra7-pcie          A  t   interrupt-controller                                   ,           A            pcie_ep@51000000             =Q      (Q     LQ     (            &  ep_dbics ti_conf ep_dbics2 addr_space                                        X           g           pcie1                    
  pcie-phy0           v                             	  Qdisabled          "   ti,dra746-pcie-ep ti,dra7-pcie-ep           A  u         axi@1            simple-bus                                   Q  Q    0     0            	  Qdisabled       pcie@51800000           =Q      Q    L               rc_dbics ti_conf config               c         d                                    Ipci       0               0               00  0                             ,                                 pcie2                    
  pcie-phy0           0                     `  C                                                                                             ti,dra746-pcie-rc ti,dra7-pcie          A  v   interrupt-controller                                   ,           A               ocmcram@40300000          
   mmio-sram           =@0                 @0                                      A  w   sram-hs@0            ti,secure-ram           =                 ocmcram@40400000          	  Qdisabled          
   mmio-sram           =@@                 @@                                      A  x      ocmcram@40500000          	  Qdisabled          
   mmio-sram           =@P                 @P                                      A  y      bandgap@4a0021e0          0  =J !   J #,   J #   ,J #   <J %d   J %t   P         ti,dra752-bandgap                  y                      A         dsp_system@40d00000          syscon          =@             A         padconf@4844a000             ti,dra7-iodelay         =HD                                     q           A  z   mmc1_iodelay_ddr_rev11_conf             <             $      X  (          ,   7      0     x  4          8          <      <  @          D          H      <  L          P          T          X          \                A         mmc1_iodelay_ddr50_rev20_conf               4  J           $        (          ,          0        4          8         <         @          D          H        L          P          T          X          \                A         mmc1_iodelay_sdr104_rev11_conf               '     (          ,         4          8          @          D         L          P          X          \                A         mmc1_iodelay_sdr104_rev20_conf               X    (          ,          4          8         @          D          L          P          X          \                A         mmc2_iodelay_hs200_rev11_conf               m  X    ,          X             ,  X               X     <        <        X                X     x          X             5  X      <      d    X  h               A         mmc2_iodelay_hs200_rev20_conf                                         I                 s        y         /              m                                                                 .      d        h   L            A         mmc2_iodelay_ddr_3_3v_rev11_conf         \           x                       	  h                            x                            x                              o                                                         "             x               x         x                          `          d          h               A  {      mmc2_iodelay_ddr_1_8v_rev11_conf         \                                                                  <                            <                          h    o            x                                             "             <               x         y   <                       `          d          h               A         mmc3_iodelay_manual1_conf             x                                                                                                                                                                        A  |      mmc4_iodelay_ds_rev11_conf            @          H          L   `      P          T          p  F      t          x          |                              1                            L                                A         mmc4_iodelay_ds_rev20_conf            @          H          L  3      P          T          p        t          x          |  e                                                        C                                A         mmc4_iodelay_sdr12_hs_sdr25_rev11_conf            @          H  
[      L  $      P          T          p  y      t          x          |                              c                                                            A         mmc4_iodelay_sdr12_hs_sdr25_rev20_conf            @          H  {      L  *      P          T          p  u      t          x          |     @                                                   |   ,                            A            dma-controller@4a056000          ti,omap4430-sdma            =J`          0                             	          
                                             dma_system          A         edma@43300000            ti,edma3-tpcc           tpcc            =C0           	  edma3_cc          $        i         h         g         '  edma3_ccint edma3_mperr edma3_ccerrint             @                                        A         tptc@43400000            ti,edma3-tptc           tptc0           =C@                   r           edma3_tcerrint          A         tptc@43500000            ti,edma3-tptc           tptc1           =CP                   s           edma3_tcerrint          A         gpio@4ae10000            ti,omap4-gpio           =J                               gpio1                                        ,           A  }      gpio@48055000            ti,omap4-gpio           =HP                              gpio2                                        ,           A  ~      gpio@48057000            ti,omap4-gpio           =Hp                              gpio3                                        ,           A        gpio@48059000            ti,omap4-gpio           =H                              gpio4                                        ,           A        gpio@4805b000            ti,omap4-gpio           =H                              gpio5                                        ,           A         gpio@4805d000            ti,omap4-gpio           =H                              gpio6                                        ,           A         gpio@48051000            ti,omap4-gpio           =H                              gpio7                                        ,                             A        gpio@48053000            ti,omap4-gpio           =H0                   t           gpio8                                        ,           A        serial@4806a000          ti,dra742-uart ti,omap4-uart            =H                      C                uart1           l         Qokay            "      1      2        'tx rx           A        serial@4806c000          ti,dra742-uart ti,omap4-uart            =H                   D           uart2           l         Qokay            "      3      4        'tx rx           A        serial@48020000          ti,dra742-uart ti,omap4-uart            =H                    E           uart3           l         Qokay            "      5      6        'tx rx           A        serial@4806e000          ti,dra742-uart ti,omap4-uart            =H                   A           uart4           l       	  Qdisabled            "      7      8        'tx rx           A        serial@48066000          ti,dra742-uart ti,omap4-uart            =H`                   d           uart5           l       	  Qdisabled            "      ?      @        'tx rx           A        serial@48068000          ti,dra742-uart ti,omap4-uart            =H                   e           uart6           l       	  Qdisabled            "      O      P        'tx rx           A        serial@48420000          ti,dra742-uart ti,omap4-uart            =HB                               uart7           l       	  Qdisabled            A        serial@48422000          ti,dra742-uart ti,omap4-uart            =HB                               uart8           l       	  Qdisabled            A        serial@48424000          ti,dra742-uart ti,omap4-uart            =HB@                              uart9           l       	  Qdisabled            A        serial@4ae2b000          ti,dra742-uart ti,omap4-uart            =J                              uart10          l       	  Qdisabled            A        mailbox@4a0f4000             ti,omap4-mailbox            =J@          $                                      	  mailbox1            1           =           O         	  Qdisabled            A        mailbox@4883a000             ti,omap4-mailbox            =H          0                                                	  mailbox2            1           =           O         	  Qdisabled            A        mailbox@4883c000             ti,omap4-mailbox            =H          0                                                	  mailbox3            1           =           O         	  Qdisabled            A        mailbox@4883e000             ti,omap4-mailbox            =H          0                                                	  mailbox4            1           =           O         	  Qdisabled            A        mailbox@48840000             ti,omap4-mailbox            =H           0                                                	  mailbox5            1           =           O           Qokay            A      mbox_ipu1_ipc3x         a                 l                 Qokay            A         mbox_dsp1_ipc3x         a                 l                 Qokay            A            mailbox@48842000             ti,omap4-mailbox            =H           0                                                	  mailbox6            1           =           O           Qokay            A      mbox_ipu2_ipc3x         a                 l                 Qokay            A         mbox_dsp2_ipc3x         a                 l                 Qokay            A            mailbox@48844000             ti,omap4-mailbox            =H@          0                                            	  mailbox7            1           =           O         	  Qdisabled            A        mailbox@48846000             ti,omap4-mailbox            =H`          0                                            	  mailbox8            1           =           O         	  Qdisabled            A        mailbox@4885e000             ti,omap4-mailbox            =H          0        	         
                           	  mailbox9            1           =           O         	  Qdisabled            A        mailbox@48860000             ti,omap4-mailbox            =H           0                                            
  mailbox10           1           =           O         	  Qdisabled            A        mailbox@48862000             ti,omap4-mailbox            =H           0                                            
  mailbox11           1           =           O         	  Qdisabled            A        mailbox@48864000             ti,omap4-mailbox            =H@          0                                            
  mailbox12           1           =           O         	  Qdisabled            A        mailbox@48802000             ti,omap4-mailbox            =H           0        {         |         }         ~         
  mailbox13           1           =           O         	  Qdisabled            A        timer@4ae18000           ti,omap5430-timer           =J                               timer1           w        pfck         i                  A        timer@48032000           ti,omap5430-timer           =H                    !           timer2          i   W   8           pfck         A        timer@48034000           ti,omap5430-timer           =H@                   "           timer3          i   W   @           pfck         A         timer@48036000           ti,omap5430-timer           =H`                   #           timer4          i   W   H           pfck         A         timer@48820000           ti,omap5430-timer           =H                    $           timer5          i                 pfck         A         timer@48822000           ti,omap5430-timer           =H                    %           timer6          i                  pfck         A         timer@48824000           ti,omap5430-timer           =H@                   &           timer7          i      (           pfck         A         timer@48826000           ti,omap5430-timer           =H`                   '           timer8          i      0           pfck         A         timer@4803e000           ti,omap5430-timer           =H                   (           timer9          i   W   P           pfck         A         timer@48086000           ti,omap5430-timer           =H`                   )           timer10         i   W   (           pfck         A         timer@48088000           ti,omap5430-timer           =H                   *           timer11         i   W   0           pfck         A         timer@4ae20000           ti,omap5430-timer           =J                    Z           timer12          w                 i      (           pfck         A        timer@48828000           ti,omap5430-timer           =H                  S           timer13         i   W              pfck         A         timer@4882a000           ti,omap5430-timer           =H                  T           timer14         i   W              pfck         A        timer@4882c000           ti,omap5430-timer           =H                  U           timer15         i   W              pfck         A        timer@4882e000           ti,omap5430-timer           =H                  V           timer16         i   W  0           pfck         A        wdt@4ae14000             ti,omap3-wdt            =J@                   K         
  wd_timer2           A        spinlock@4a0f6000            ti,omap4-hwspinlock         =J`          	  spinlock                       A        dmm@4e000000             ti,omap5-dmm            =N                     l           dmm       ipu@58820000             ti,dra7-ipu         =X             l2ram           ipu1                       J U         Qokay                                                              A        ipu@55020000             ti,dra7-ipu         =U             l2ram           ipu2                       J          Qokay                                                              A        dsp@40800000             ti,dra7-dsp         =@    @     @             l2ram l1pram l1dram         dsp1               	  \                      J T         Qokay                                                           A        i2c@48070000             ti,omap4-i2c            =H                    3                                     i2c1            Qokay                     A     edt-ft5506@38                          &  }        A           *          *          *w                 =   8         edt,edt-ft5506 edt,edt-ft5x06          Qokay         gpio@27         A                              =   '         nxp,pcf8575       tlc59116@40         A          =   @         ti,tlc59108                              bl@2            A          =         
  	backlight e          tc358768@0e         A          *w                 prefclk         i                                    =            toshiba,tc358768      display         A  #        ++          	lcd         =             osd,osd101t2587-53ts      port       endpoint            A  "          !            ports           A                               port@1          =      endpoint            A  !          "         port@0          =       endpoint            A          *                            tps659038@58             ti,tps659038            =   X                          A     tps659038_pmic           ti,tps659038-pmic      regulators     smps123         smps123         ' P        ?          4         H        A         smps45          smps45          ' P        ?          4         H        A        smps6           smps6           ' P        ?          4         H        A        smps7           smps7           ' P        ? 0         4         H        A        smps8           smps8           ' P        ?          4         H        A        smps9           smps9           ' w@        ? w@         4         H        A        ldo1            ldo1            ' w@        ? 2Z         4         H        A         ldo2            ldo2            ' 2Z        ? 2Z         4         H        A        ldo3            ldo3            ' w@        ? w@         4         H        A         ldo9            ldo9            '         ?          4         H         Z        A        ldoln           ldoln           ' w@        ? w@         4         H        A         ldousb          ldousb          ' 2Z        ? 2Z         H        A         regen2          regen2           H         4        A        sysen1          sysen1           H         4        A        sysen2          sysen2           H         4        A                 gpio@20          ti,pcf8575 nxp,pcf8575          =                                 &                                  ,           A        gpio@21          ti,pcf8575 nxp,pcf8575          =   !        q                               &                                  ,           A         tlv320aic3106@19                         ti,tlv320aic3106            =              (                   Qokay                                                        A            i2c@48072000             ti,omap4-i2c            =H                    4                                     i2c2            Qokay                     A     gpio@26          ti,pcf8575 nxp,pcf8575          =   &                            A      p1                                           vin6_sel_s0          ov10633@37           ovti,ov10633            =   7        i           pxvclk                       port       endpoint                       %           2           ?            A                  i2c@48060000             ti,omap4-i2c            =H                    8                                     i2c3            Qokay                     A        i2c@4807a000             ti,omap4-i2c            =H                   9                                     i2c4          	  Qdisabled            A        i2c@4807c000             ti,omap4-i2c            =H                   7                                     i2c5          	  Qdisabled            A        mmc@4809c000             ti,dra7-sdhci           =H	                   N           mmc1            Qokay            K           Xq          f         s                                                        C  default hs sdr12 sdr25 sdr50 ddr50-rev11 sdr104-rev11 ddr50 sdr104                                                                                                            
              A        1w@480b2000          ti,omap3-1w         =H                    5           hdq1w           A        mmc@480b4000             ti,dra7-sdhci           =H@                   Q           mmc2            Qokay            Xq                         $         f         s                                          3      ?  default hs ddr_1_8v-rev11 ddr_1_8v hs200_1_8v-rev11 hs200_1_8v                                                                                     A        mmc@480ad000             ti,dra7-sdhci           =H
                   Y           mmc3          	  Qdisabled            XА              @          A        mmc@480d1000             ti,dra7-sdhci           =H                   [           mmc4            Qokay            Xq              @                      A         T         3                                                      F  default-rev11 default hs-rev11 hs sdr12-rev11 sdr12 sdr25-rev11 sdr25                                                                                                                            A     wifi@2        
   ti,wl1835           =            &                          mmu@40d01000             ti,dra7-dsp-iommu           =@                            
  mmu0_dsp1           j            w               A         mmu@40d02000             ti,dra7-dsp-iommu           =@                             
  mmu1_dsp1           j            w              A         mmu@58882000             ti,dra7-iommu           =X                            	  mmu_ipu1            j                     A         mmu@55082000             ti,dra7-iommu           =U                            	  mmu_ipu2            j                     A         pruss-soc-bus@4b226004           ti,am5728-pruss-soc-bus         =K"`           pruss1                                          	  Qdisabled            A     pruss@4b200000           ti,am5728-pruss         =K            `                                                                                        0  host2 host3 host4 host5 host6 host7 host8 host9                                         	  Qdisabled            A     memories@4b200000           =K       K       K!             dram0 dram1 shrdram2            A        cfg@4b226000             syscon          =K"`             A        iep@4b22e000             syscon          =K"           A        mii-rt@4b232000          syscon          =K#     X        A        interrupt-controller@4b220000            ti,am5728-pruss-intc            =K"                       ,           A         pru@4b234000             ti,am5728-pru           =K#@   0 K"     K"$            iram control debug          am57xx-pru1_0-fw             &                         vring kick          A        pru@4b238000             ti,am5728-pru           =K#   0 K"@    K"D            iram control debug          am57xx-pru1_1-fw             &                         vring kick          A        mdio@4b232400            ti,davinci_mdio         =K#$                                      i           pfck          B@      	  Qdisabled            A              pruss-soc-bus@4b2a6004           ti,am5728-pruss-soc-bus         =K*`           pruss2                                          	  Qdisabled            A     pruss@4b280000           ti,am5728-pruss         =K(           `                                                                                        0  host2 host3 host4 host5 host6 host7 host8 host9                                         	  Qdisabled            A     memories@4b280000           =K(      K(      K)             dram0 dram1 shrdram2            A        cfg@4b2a6000             syscon          =K*`             A        iep@4b2ae000             syscon          =K*           A        mii-rt@4b2b2000          syscon          =K+     X        A        interrupt-controller@4b2a0000            ti,am5728-pruss-intc            =K*                       ,           A         pru@4b2b4000             ti,am5728-pru           =K+@   0 K*     K*$            iram control debug          am57xx-pru2_0-fw             &                         vring kick          A        pru@4b2b8000             ti,am5728-pru           =K+   0 K*@    K*D            iram control debug          am57xx-pru2_1-fw             &                         vring kick          A        mdio@4b2b2400            ti,davinci_mdio         =K+$                                      i           pfck          B@      	  Qdisabled            A              regulator-abb-mpu         
   ti,abb-v3           abb_mpu                                    i              2                 (  =J}   J}   J`   J ;    JX         D  setup-address control-address int-address efuse-address ldo-address                               	
         H  	 ,                  @                 v                        A         regulator-abb-ivahd       
   ti,abb-v3         
  abb_ivahd                                      i              2                 (  =J~4   J~$   J`   J %   J $p         D  setup-address control-address int-address efuse-address ldo-address         @                      	
         H  	                   0                                         A        regulator-abb-dspeve          
   ti,abb-v3           abb_dspeve                                     i              2                 (  =J~0   J~    J`   J %   J $l         D  setup-address control-address int-address efuse-address ldo-address                                	
         H  	                   0                                         A        regulator-abb-gpu         
   ti,abb-v3           abb_gpu                                    i              2                 (  =J}   J}   J`   J ;   JT         D  setup-address control-address int-address efuse-address ldo-address                               	
         H  	                   v                                          A        spi@48098000             ti,omap4-mcspi          =H	                   <                                     mcspi1          	*         @  "      #      $      %      &      '      (      )      *         'tx0 rx0 tx1 rx1 tx2 rx2 tx3 rx3         Qokay            A        spi@4809a000             ti,omap4-mcspi          =H	                   =                                     mcspi2          	*            "      +      ,      -      .        'tx0 rx0 tx1 rx1         Qokay            A        spi@480b8000             ti,omap4-mcspi          =H                   V                                     mcspi3          	*           "                    'tx0 rx0       	  Qdisabled            A        spi@480ba000             ti,omap4-mcspi          =H                   +                                     mcspi4          	*           "      F      G        'tx0 rx0       	  Qdisabled            A        qspi@4b300000            ti,dra7xxx-qspi         =K0     \              qspi_base qspi_mmap         	8   	  X                                  qspi            i   W  8           pfck         	1                 W           Qokay            	K         A     m25p80@0             s25fl256s1          	K         =            	]           	n                               partition@0       	  	QSPI.SPL            =             partition@1         	QSPI.SPL.backup1            =            partition@2         	QSPI.SPL.backup2            =            partition@3         	QSPI.SPL.backup3            =            partition@4         	QSPI.u-boot         =            partition@5         	QSPI.u-boot-spl-os          =            partition@6         	QSPI.u-boot-env         =            partition@7         	QSPI.u-boot-env.backup1         =            partition@8         	QSPI.kernel         =            partition@9         	QSPI.file-system            =   b              ocp2scp@4a090000             ti,omap-ocp2scp                                           =J	            	  ocp2scp3       phy@4a096000             ti,phy-pipe3-sata           =J	`    J	d    dJ	h    @        phy_rx phy_tx pll_ctrl          	   	  t        i         h           psysclk refclk           	   	          	            A         pciephy@4a094000             ti,phy-pipe3-pcie           =J	@    J	D    d        phy_rx phy_tx           	              	            4  i   >   ?                  	         
            ;  pdpll_ref dpll_ref_m2 wkupclk refclk div-clk phy-div sysclk          	            A         pciephy@4a095000             ti,phy-pipe3-pcie           =J	P    J	T    d        phy_rx phy_tx           	               	            4  i   >   ?                  	         
            ;  pdpll_ref dpll_ref_m2 wkupclk refclk div-clk phy-div sysclk          	          	  Qdisabled            A            sata@4a141100            snps,dwc-ahci           =J     J                   1                    	  sata-phy            i      h           sata            	           A        rtc@48838000             ti,am3352-rtc           =H                                        rtcss           i   P        A        ocp2scp@4a080000             ti,omap-ocp2scp                                           =J            	  ocp2scp1       phy@4a084000             ti,dra7x-usb2 ti,omap-usb2          =J@            	   	           i                    pwkupclk refclk          	            	           A         phy@4a085000              ti,dra7x-usb2-phy2 ti,omap-usb2         =JP            	   	  t        i                     pwkupclk refclk          	            	           A         phy@4a084400             ti,omap-usb3            =JD    JH    dJL    @        phy_rx phy_tx pll_ctrl          	   	  p        i                       pwkupclk sysclk refclk           	            A            target-module@4a0dd000           ti,sysc-omap4-sr ti,sysc            smartreflex_core            =J8           sysc            	           	                     i                  pfck                                      J          target-module@4a0d9000           ti,sysc-omap4-sr ti,sysc            smartreflex_mpu         =J8           sysc            	           	                     i                  pfck                                      J          omap_dwc3_1@48880000             ti,dwc3         usb_otg_ss1         =H                    H                                    	                    	           A     usb@48890000          
   snps,dwc3           =H   p       $         G          G          H           peripheral host otg                       usb2-phy usb3-phy           
super-speed         
otg          
         
4        	           A           omap_dwc3_2@488c0000             ti,dwc3         usb_otg_ss2         =H                    W                                    	                    	           A     usb@488d0000          
   snps,dwc3           =H   p       $         I          I          W           peripheral host otg                  	  usb2-phy            
high-speed          
host             
         
4         
M        	           A           omap_dwc3_3@48900000             ti,dwc3         usb_otg_ss3         =H                   X                                    	                  	  Qdisabled            A     usb@48910000          
   snps,dwc3           =H   p       $         X          X         X           peripheral host otg         
high-speed          
otg          
         
4        A           elm@48078000             ti,am3352-elm           =H                             elm         Qokay            A         gpmc@50000000            ti,am3352-gpmc          gpmc            =P     |                          "                  'rxtx            
j           
v                                             ,                             	  Qdisabled                                  A      nand@0,0             ti,omap2-nand           =                    &                                  
                   
prefetch-dma            
bch8            
           
           
           
            
            
   P           P        !            0   <        C   <        V   
        d   2        s              (           (           P           P           P                                                                            partition@0       	  	NAND.SPL            =             partition@1         	NAND.SPL.backup1            =            partition@2         	NAND.SPL.backup2            =            partition@3         	NAND.SPL.backup3            =            partition@4         	NAND.u-boot-spl-os          =            partition@5         	NAND.u-boot         =            partition@6         	NAND.u-boot-env         =            partition@7         	NAND.u-boot-env.backup1         =            partition@8         	NAND.kernel         =             partition@9         	NAND.file-system            =   `              atl@4843c000             ti,dra7-atl         =HC           atl         3                    i                  pfck         Qokay               a                              `   d                
@   V"         A     atl2            F           J            mcasp@48460000           ti,dra7-mcasp-audio         mcasp1          =HF      E             mpu dat                h          g           tx rx           "                          'tx rx         $  i                                   pfck ahclkx ahclkr         	  Qdisabled            A        mcasp@48464000           ti,dra7-mcasp-audio         mcasp2          =HF@     E             mpu dat                                     tx rx           "                          'tx rx         $  i   W  `      W  `      W  `           pfck ahclkx ahclkr         	  Qdisabled            A        mcasp@48468000           ti,dra7-mcasp-audio         mcasp3          =HF     F              mpu dat                                     tx rx           "                          'tx rx           i   W  h      W  h           pfck ahclkx          Qokay                           W  h                      N            V           `                      k            v            A         mcasp@4846c000           ti,dra7-mcasp-audio         mcasp4          =HF     HC`            mpu dat                                     tx rx           "                          'tx rx           i   W        W             pfck ahclkx        	  Qdisabled            A        mcasp@48470000           ti,dra7-mcasp-audio         mcasp5          =HG      HC            mpu dat                                     tx rx           "                          'tx rx           i   W  x      W  x           pfck ahclkx        	  Qdisabled            A        mcasp@48474000           ti,dra7-mcasp-audio         mcasp6          =HG@     HD            mpu dat                                     tx rx           "                          'tx rx           i   W        W             pfck ahclkx        	  Qdisabled            A        mcasp@48478000           ti,dra7-mcasp-audio         mcasp7          =HG     HE             mpu dat                                     tx rx           "                          'tx rx           i   W        W             pfck ahclkx        	  Qdisabled            A        mcasp@4847c000           ti,dra7-mcasp-audio         mcasp8          =HG     HE@            mpu dat                                     tx rx           "                          'tx rx           i   W        W             pfck ahclkx          Qokay            default                                        A        crossbar@4a002a48            ti,irq-crossbar         =J *H  0                  &           ,                                                                                
                             A         ethernet@48484000            ti,dra7-cpsw ti,cpsw            gmac            i                  	  pfck cpts                                                                                 'xL        7           =HH@    HHR   .                                   H      0        N         O         P         Q                       	        Qokay             S        A     mdio@48485000            ti,cpsw-mdio ti,davinci_mdio                                      davinci_mdio             B@        =HHP            A         slave@48480200          ]                i              prgmii           y           A        slave@48480300          ]                i              prgmii           y           A        cpsw-phy-sel@4a002554            ti,dra7xx-cpsw-phy-sel          =J %T         	  gmii-sel            A           can@4ae3c000             ti,dra7-d_can           dcan1           =J                	  X                              i      h           Qok          default sleep active                                             A        can@48480000             ti,dra7-d_can           dcan2           =HH                 	  X                             i           Qok          default sleep                                 A        gpu@56000000             ti,dra7-sgx544 img,sgx544           =V              gpu_ocp_base                              gpu         i   
   S   T        piclk fclk1 fclk2            Qok          A        bb2d@59000000            ti,dra7-bb2d            =Y                     x           bb2d            i                  pfck         Qokay            A        dss@58000000             ti,dra7-dss         Qok        	  dss_core               	  8                                        (  =X      X @T   X C     X T   X            (  dss pll1_clkctrl pll1 pll2_clkctrl pll2       $  i                                      pfck video1_clk video2_clk                      A     ports                                port@0          =       endpoint            A          *                         dispc@58001000           ti,dra7-dispc           =X                             
  dss_dispc           i                  pfck            	  4      encoder@58060000             ti,dra7-hdmi             =X     X    X    X            wp pll phy core                `           Qok        	  dss_hdmi            i          	          
        pfck sys_clk         "      L      	  'audio_tx                       A     port       endpoint                       A                 epwmss@4843e000           ti,dra746-pwmss ti,am33xx-pwmss         =HC    0        epwmss0                                	  Qdisabled                     A     pwm@4843e200          "   ti,dra746-ehrpwm ti,am3352-ehrpwm                      =HC            i            
  ptbclk fck         	  Qdisabled            A        ecap@4843e100            ti,dra746-ecap ti,am3352-ecap                      =HC            i           pfck       	  Qdisabled            A           epwmss@48440000           ti,dra746-pwmss ti,am33xx-pwmss         =HD     0        epwmss1                                	  Qdisabled                     A     pwm@48440200          "   ti,dra746-ehrpwm ti,am3352-ehrpwm                      =HD            i            
  ptbclk fck         	  Qdisabled            A        ecap@48440100            ti,dra746-ecap ti,am3352-ecap                      =HD            i           pfck       	  Qdisabled            A           epwmss@48442000           ti,dra746-pwmss ti,am33xx-pwmss         =HD     0        epwmss2                                	  Qdisabled                     A     pwm@48442200          "   ti,dra746-ehrpwm ti,am3352-ehrpwm                      =HD"            i            
  ptbclk fck         	  Qdisabled            A        ecap@48442100            ti,dra746-ecap ti,am3352-ecap                      =HD!            i           pfck       	  Qdisabled            A           aes@4b500000             ti,omap4-aes            aes1            =KP                    P           "      o          n            'tx rx           i   
        pfck         A        aes@4b700000             ti,omap4-aes            aes2            =Kp                    ;           "      r          q            'tx rx           i   
        pfck         A        des@480a5000             ti,omap4-des            des         =H
P                   M           "      u      t        'tx rx           i   
        pfck         A        sham@53100000            ti,omap5-sham           sham            =K                   .           "      w            'rx          i   
        pfck         A        rng@48090000             ti,omap4-rng            rng         =H	                     /           i   
        pfck         A        opp-supply@4a003b20          ti,omap5-opp-supply         =J ;             ,     @    v            `        A        vpe          ti,vpe          vpe         i   V        pfck          =H     H    HW    H            vpe_top sc csc vpdma                  b                                   vip@0x48970000           ti,vip1       @  =H    HU    HW    HX    HZ    H\    H]    H          ,  vip parser0 csc0 sc0 parser1 csc1 sc1 vpdma         vip1                  _                       	  4                                  Qokay            A     ports                                port@0          =            A     endpoint@0                              A            port@1          =           A        port@2          =           A        port@3          =           A              dsp_system@41500000          syscon          =AP             A         omap_dwc3_4@48940000             ti,dwc3         usb_otg_ss4         =H                   Z                                    	                  	  Qdisabled            A     usb@48950000          
   snps,dwc3           =H   p       $        Y         Y         Z           peripheral host otg         
high-speed          
otg         A           mmu@41501000             ti,dra7-dsp-iommu           =AP                            
  mmu0_dsp2           j            w               A         mmu@41502000             ti,dra7-dsp-iommu           =AP                             
  mmu1_dsp2           j            w              A         dsp@41000000             ti,dra7-dsp         =A     A`     Ap             l2ram l1pram l1dram         dsp2               	  `                      J V         Qokay                                                           A        vip@0x48990000           ti,vip2       @  =H    HU    HW    HX    HZ    H\    H]    H          ,  vip parser0 csc0 sc0 parser1 csc1 sc1 vpdma         vip2                  `                       	  4                                	  Qdisabled            A     ports                                port@0          =            A        port@1          =           A        port@2          =           A         port@3          =           A              vip@0x489b0000           ti,vip3       @  =H    HU    HW    HX    HZ    H\    H]    H          ,  vip parser0 csc0 sc0 parser1 csc1 sc1 vpdma         vip3                  a                       	  4                                	  Qdisabled            A     ports                                port@0          =            A        port@1          =           A                 thermal-zones           A     cpu_thermal                    -          ;               K              A     trips           A     cpu_alert           X         d          Ppassive         A         cpu_crit            X         d        	  Pcritical            A           cooling-maps            A  	   map0            o           t               gpu_thermal                    -          ;              K              A  
   trips      gpu_crit            X         d        	  Pcritical            A              core_thermal                       -          ;              K              A     trips      core_crit           X         d        	  Pcritical            A              dspeve_thermal                     -          ;              K              A     trips      dspeve_crit         X         d        	  Pcritical            A              iva_thermal                    -          ;              K              A     trips      iva_crit            X         d        	  Pcritical            A                 pmu          arm,cortex-a15-pmu           &                                     extcon_usb1          linux,extcon-usb-gpio                             A         extcon_usb2          linux,extcon-usb-gpio                             A         sound0           simple-audio-card           DRA7xx-EVM        H  Headphone Headphone Jack Line Line Out Microphone Mic Jack Line Line In         Headphone Jack HPLOUT Headphone Jack HPROUT Line Out LLOUT Line Out RLOUT MIC3L Mic Jack MIC3R Mic Jack Mic Jack Mic Bias LINE1L Line In LINE1R Line In         dsp_b                                  0        A     simple-audio-card,cpu           U           _ V"         A         simple-audio-card,codec         U           i            leds          
   gpio-leds      led0          
  	dra7:usr1                           voff       led1          
  	dra7:usr2                           voff       led2          
  	dra7:usr3                           voff       led3          
  	dra7:usr4                           voff          gpio_keys         
   gpio-keys                                         USER1         	  	btnUser1                                     USER2         	  	btnUser2                                       clk_ov10633_fixed           W             fixed-clock         n6         A         memory@0            Imemory          =           `         fixedregulator-evm_12v0          regulator-fixed       	  evm_12v0            '          ?           4         H        A        fixedregulator-evm_1v8           regulator-fixed         evm_1v8                   ' w@        ? w@        A         reserved-memory                                      ipu2-memory@95800000             shared-dma-pool         =                             Qokay            A         dsp1-memory@99000000             shared-dma-pool         =                               Qokay            A         ipu1-memory@9d000000             shared-dma-pool         =                               Qokay            A         dsp2-memory@9f000000             shared-dma-pool         =                               Qokay            A            fixedregulator-sd            regulator-fixed         evm_3v3_sd          ' 2Z        ? 2Z                                   A         fixedregulator-evm_3v3_sw            regulator-fixed         evm_3v3_sw                    ' 2Z        ? 2Z        A         fixedregulator-aic_dvdd          regulator-fixed       	  aic_dvdd                       ' w@        ? w@        A         fixedregulator-evm3v3            regulator-fixed         evm_3v3         ' 2Z        ? 2Z                   4         H        A        fixedregulator-evm_5v0           regulator-fixed         evm_5v0         ' LK@        ? LK@                   4         H        A        fixedregulator-evm_3v6           regulator-fixed         evm_3v6         ' 6        ? 6                   4         H        A         fixedregulator-mmcwl             regulator-fixed         vmmcwl_fixed            ' w@        ? w@                           p                 A         fixedregulator-vtt           regulator-fixed       
  vtt_fixed           ' p        ? p         4         H                                            A        connector@1          hdmi-connector          	hdmi            Pa           A     port       endpoint                      A              encoder@1            ti,dra7evm-tpd12s015            i2c ddc           	          
                0                                                A     ports                                port@0          =       endpoint@0                    A            port@1          =      endpoint@0                    A                 __symbols__       5  +</ocp/i2c@48070000/tc358768@0e/ports/port@1/endpoint  ocp      5  +5/ocp/i2c@48070000/tc358768@0e/display/port/endpoint  ocp      '  $/ocp/i2c@48070000/tc358768@0e/display         )  +#/ocp/dss@58000000/ports/port@0/endpoint          !  +/ocp/i2c@48070000/edt-ft5506@38    $        +/ocp/i2c@48070000/gpio@27  4      $  */ocp/i2c@48070000/tlc59116@40/bl@2          */ocp/i2c@48070000/tlc59116@40  o      5  */ocp/i2c@48070000/tc358768@0e/ports/port@0/endpoint  ocp      %  */ocp/i2c@48070000/tc358768@0e/ports            */ocp/i2c@48070000/tc358768@0e          */tc358768_refclk           */backlight          /interrupt-controller@48211000          /interrupt-controller@48281000          /cpus/cpu@0         /opp-table           /ocp/l4@4a000000            /ocp/l4@4a000000/scm@2000         %  /ocp/l4@4a000000/scm@2000/scm_conf@0          9  /ocp/l4@4a000000/scm@2000/scm_conf@0/pbias_regulator@e00          I  $/ocp/l4@4a000000/scm@2000/scm_conf@0/pbias_regulator@e00/pbias_mmc_omap5          ,  2/ocp/l4@4a000000/scm@2000/scm_conf@0/clocks       @  B/ocp/l4@4a000000/scm@2000/scm_conf@0/clocks/dss_deshdcp_clk@558       >  R/ocp/l4@4a000000/scm@2000/scm_conf@0/clocks/ehrpwm0_tbclk@558         >  `/ocp/l4@4a000000/scm@2000/scm_conf@0/clocks/ehrpwm1_tbclk@558         >  n/ocp/l4@4a000000/scm@2000/scm_conf@0/clocks/ehrpwm2_tbclk@558         7  |/ocp/l4@4a000000/scm@2000/scm_conf@0/clocks/sys_32k_ck        &  /ocp/l4@4a000000/scm@2000/pinmux@1400         8  /ocp/l4@4a000000/scm@2000/pinmux@1400/mmc1_pins_default       6  /ocp/l4@4a000000/scm@2000/pinmux@1400/mmc1_pins_sdr12         3  /ocp/l4@4a000000/scm@2000/pinmux@1400/mmc1_pins_hs        6  /ocp/l4@4a000000/scm@2000/pinmux@1400/mmc1_pins_sdr25         6  /ocp/l4@4a000000/scm@2000/pinmux@1400/mmc1_pins_sdr50         6  /ocp/l4@4a000000/scm@2000/pinmux@1400/mmc1_pins_ddr50         7  /ocp/l4@4a000000/scm@2000/pinmux@1400/mmc1_pins_sdr104        8  /ocp/l4@4a000000/scm@2000/pinmux@1400/mmc2_pins_default       3  /ocp/l4@4a000000/scm@2000/pinmux@1400/mmc2_pins_hs        ?  $/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc2_pins_ddr_3_3v_rev11        ?  =/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc2_pins_ddr_1_8v_rev11        :  V/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc2_pins_ddr_rev20         6  j/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc2_pins_hs200         8  z/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc4_pins_default       3  /ocp/l4@4a000000/scm@2000/pinmux@1400/mmc4_pins_hs        8  /ocp/l4@4a000000/scm@2000/pinmux@1400/mmc3_pins_default       3  /ocp/l4@4a000000/scm@2000/pinmux@1400/mmc3_pins_hs        6  /ocp/l4@4a000000/scm@2000/pinmux@1400/mmc3_pins_sdr12         6  /ocp/l4@4a000000/scm@2000/pinmux@1400/mmc3_pins_sdr25         6  /ocp/l4@4a000000/scm@2000/pinmux@1400/mmc3_pins_sdr50         6  /ocp/l4@4a000000/scm@2000/pinmux@1400/mmc4_pins_sdr12         6  /ocp/l4@4a000000/scm@2000/pinmux@1400/mmc4_pins_sdr25         9  /ocp/l4@4a000000/scm@2000/pinmux@1400/dcan1_pins_default          7  /ocp/l4@4a000000/scm@2000/pinmux@1400/dcan1_pins_sleep        =  ,/ocp/l4@4a000000/scm@2000/pinmux@1400/pinmux_mcasp8_axr2_pin          C  </ocp/l4@4a000000/scm@2000/pinmux@1400/pinmux_hdmi_i2c_pins_default        ?  N/ocp/l4@4a000000/scm@2000/pinmux@1400/pinmux_hdmi_i2c_pins_ddc        9  `/ocp/l4@4a000000/scm@2000/pinmux@1400/dcan2_pins_default          7  s/ocp/l4@4a000000/scm@2000/pinmux@1400/dcan2_pins_sleep        (  /ocp/l4@4a000000/scm@2000/scm_conf@1c04       (  /ocp/l4@4a000000/scm@2000/scm_conf@1c24       )  /ocp/l4@4a000000/scm@2000/dma-router@b78          )  /ocp/l4@4a000000/scm@2000/dma-router@c78          "  /ocp/l4@4a000000/cm_core_aon@5000         )  /ocp/l4@4a000000/cm_core_aon@5000/clocks          7  /ocp/l4@4a000000/cm_core_aon@5000/clocks/atl_clkin0_ck        7  /ocp/l4@4a000000/cm_core_aon@5000/clocks/atl_clkin1_ck        7  /ocp/l4@4a000000/cm_core_aon@5000/clocks/atl_clkin2_ck        7  /ocp/l4@4a000000/cm_core_aon@5000/clocks/atl_clkin3_ck        7  /ocp/l4@4a000000/cm_core_aon@5000/clocks/hdmi_clkin_ck        6  /ocp/l4@4a000000/cm_core_aon@5000/clocks/mlb_clkin_ck         7  "/ocp/l4@4a000000/cm_core_aon@5000/clocks/mlbp_clkin_ck        =  0/ocp/l4@4a000000/cm_core_aon@5000/clocks/pciesref_acs_clk_ck          7  D/ocp/l4@4a000000/cm_core_aon@5000/clocks/ref_clkin0_ck        7  R/ocp/l4@4a000000/cm_core_aon@5000/clocks/ref_clkin1_ck        7  `/ocp/l4@4a000000/cm_core_aon@5000/clocks/ref_clkin2_ck        7  n/ocp/l4@4a000000/cm_core_aon@5000/clocks/ref_clkin3_ck        5  |/ocp/l4@4a000000/cm_core_aon@5000/clocks/rmii_clk_ck          9  /ocp/l4@4a000000/cm_core_aon@5000/clocks/sdvenc_clkin_ck          ?  /ocp/l4@4a000000/cm_core_aon@5000/clocks/secure_32k_clk_src_ck        >  /ocp/l4@4a000000/cm_core_aon@5000/clocks/sys_clk32_crystal_ck         =  /ocp/l4@4a000000/cm_core_aon@5000/clocks/sys_clk32_pseudo_ck          :  /ocp/l4@4a000000/cm_core_aon@5000/clocks/virt_12000000_ck         :  /ocp/l4@4a000000/cm_core_aon@5000/clocks/virt_13000000_ck         :  /ocp/l4@4a000000/cm_core_aon@5000/clocks/virt_16800000_ck         :  
/ocp/l4@4a000000/cm_core_aon@5000/clocks/virt_19200000_ck         :  /ocp/l4@4a000000/cm_core_aon@5000/clocks/virt_20000000_ck         :  ,/ocp/l4@4a000000/cm_core_aon@5000/clocks/virt_26000000_ck         :  =/ocp/l4@4a000000/cm_core_aon@5000/clocks/virt_27000000_ck         :  N/ocp/l4@4a000000/cm_core_aon@5000/clocks/virt_38400000_ck         4  _/ocp/l4@4a000000/cm_core_aon@5000/clocks/sys_clkin2       :  j/ocp/l4@4a000000/cm_core_aon@5000/clocks/usb_otg_clkin_ck         9  {/ocp/l4@4a000000/cm_core_aon@5000/clocks/video1_clkin_ck          <  /ocp/l4@4a000000/cm_core_aon@5000/clocks/video1_m2_clkin_ck       9  /ocp/l4@4a000000/cm_core_aon@5000/clocks/video2_clkin_ck          <  /ocp/l4@4a000000/cm_core_aon@5000/clocks/video2_m2_clkin_ck       9  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_abe_ck@1e0          8  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_abe_x2_ck       >  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_abe_m2x2_ck@1f0         5  /ocp/l4@4a000000/cm_core_aon@5000/clocks/abe_clk@108          <  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_abe_m2_ck@1f0       >  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_abe_m3x2_ck@1f4         ?  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_byp_mux@12c        :  '/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_ck@120         9  4/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_x2_ck          @  D/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_h12x2_ck@13c       =  W/ocp/l4@4a000000/cm_core_aon@5000/clocks/mpu_dpll_hs_clk_div          9  k/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_mpu_ck@160          <  w/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_mpu_m2_ck@170       6  /ocp/l4@4a000000/cm_core_aon@5000/clocks/mpu_dclk_div         =  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dsp_dpll_hs_clk_div          >  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_dsp_byp_mux@240         9  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_dsp_ck@234          <  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_dsp_m2_ck@244       =  /ocp/l4@4a000000/cm_core_aon@5000/clocks/iva_dpll_hs_clk_div          >  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_iva_byp_mux@1ac         9  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_iva_ck@1a0          <  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_iva_m2_ck@1b0       2  /ocp/l4@4a000000/cm_core_aon@5000/clocks/iva_dclk         >  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gpu_byp_mux@2e4         9  -/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gpu_ck@2d8          <  9/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gpu_m2_ck@2e8       =  H/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_m2_ck@130          @  X/ocp/l4@4a000000/cm_core_aon@5000/clocks/core_dpll_out_dclk_div       >  o/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_ddr_byp_mux@21c         9  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_ddr_ck@210          <  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_ddr_m2_ck@220       ?  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gmac_byp_mux@2b4        :  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gmac_ck@2a8         =  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gmac_m2_ck@2b8          9  /ocp/l4@4a000000/cm_core_aon@5000/clocks/video2_dclk_div          9  /ocp/l4@4a000000/cm_core_aon@5000/clocks/video1_dclk_div          7  /ocp/l4@4a000000/cm_core_aon@5000/clocks/hdmi_dclk_div        =  /ocp/l4@4a000000/cm_core_aon@5000/clocks/per_dpll_hs_clk_div          =  /ocp/l4@4a000000/cm_core_aon@5000/clocks/usb_dpll_hs_clk_div          =   /ocp/l4@4a000000/cm_core_aon@5000/clocks/eve_dpll_hs_clk_div          >  4/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_eve_byp_mux@290         9  E/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_eve_ck@284          <  Q/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_eve_m2_ck@294       6  `/ocp/l4@4a000000/cm_core_aon@5000/clocks/eve_dclk_div         @  m/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_h13x2_ck@140       @  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_h14x2_ck@144       @  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_h22x2_ck@154       @  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_h23x2_ck@158       @  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_h24x2_ck@15c       8  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_ddr_x2_ck       ?  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_ddr_h11x2_ck@228        8  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_dsp_x2_ck       >  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_dsp_m3x2_ck@248         9  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gmac_x2_ck          @  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gmac_h11x2_ck@2c0       @  0/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gmac_h12x2_ck@2c4       @  C/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gmac_h13x2_ck@2c8       ?  V/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gmac_m3x2_ck@2bc        8  h/ocp/l4@4a000000/cm_core_aon@5000/clocks/gmii_m_clk_div       7  w/ocp/l4@4a000000/cm_core_aon@5000/clocks/hdmi_clk2_div        6  /ocp/l4@4a000000/cm_core_aon@5000/clocks/hdmi_div_clk         9  /ocp/l4@4a000000/cm_core_aon@5000/clocks/l3_iclk_div@100          9  /ocp/l4@4a000000/cm_core_aon@5000/clocks/l4_root_clk_div          9  /ocp/l4@4a000000/cm_core_aon@5000/clocks/video1_clk2_div          8  /ocp/l4@4a000000/cm_core_aon@5000/clocks/video1_div_clk       9  /ocp/l4@4a000000/cm_core_aon@5000/clocks/video2_clk2_div          8  /ocp/l4@4a000000/cm_core_aon@5000/clocks/video2_div_clk       2  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dummy_ck         /  /ocp/l4@4a000000/cm_core_aon@5000/clockdomains        -  /ocp/l4@4a000000/cm_core_aon@5000/mpu_cm@300          4  /ocp/l4@4a000000/cm_core_aon@5000/mpu_cm@300/clk@20       .  !/ocp/l4@4a000000/cm_core_aon@5000/dsp1_cm@400         5  )/ocp/l4@4a000000/cm_core_aon@5000/dsp1_cm@400/clk@20          .  6/ocp/l4@4a000000/cm_core_aon@5000/ipu1_cm@500         5  >/ocp/l4@4a000000/cm_core_aon@5000/ipu1_cm@500/clk@20          -  K/ocp/l4@4a000000/cm_core_aon@5000/ipu_cm@540          3  R/ocp/l4@4a000000/cm_core_aon@5000/ipu_cm@540/clk@0        .  ^/ocp/l4@4a000000/cm_core_aon@5000/dsp2_cm@600         5  f/ocp/l4@4a000000/cm_core_aon@5000/dsp2_cm@600/clk@20          -  s/ocp/l4@4a000000/cm_core_aon@5000/rtc_cm@700          4  z/ocp/l4@4a000000/cm_core_aon@5000/rtc_cm@700/clk@40         /ocp/l4@4a000000/cm_core@8000         %  /ocp/l4@4a000000/cm_core@8000/clocks          :  /ocp/l4@4a000000/cm_core@8000/clocks/dpll_pcie_ref_ck@200         @  /ocp/l4@4a000000/cm_core@8000/clocks/dpll_pcie_ref_m2ldo_ck@210       C  /ocp/l4@4a000000/cm_core@8000/clocks/apll_pcie_in_clk_mux@4ae06118        6  /ocp/l4@4a000000/cm_core@8000/clocks/apll_pcie_ck@21c         B  /ocp/l4@4a000000/cm_core@8000/clocks/optfclk_pciephy_div@4a00821c         9  /ocp/l4@4a000000/cm_core@8000/clocks/apll_pcie_clkvcoldo          =  /ocp/l4@4a000000/cm_core@8000/clocks/apll_pcie_clkvcoldo_div          5  '/ocp/l4@4a000000/cm_core@8000/clocks/apll_pcie_m2_ck          :  7/ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_byp_mux@14c         5  H/ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_ck@140          8  T/ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_m2_ck@150       ;  c/ocp/l4@4a000000/cm_core@8000/clocks/func_96m_aon_dclk_div        :  y/ocp/l4@4a000000/cm_core@8000/clocks/dpll_usb_byp_mux@18c         5  /ocp/l4@4a000000/cm_core@8000/clocks/dpll_usb_ck@180          8  /ocp/l4@4a000000/cm_core@8000/clocks/dpll_usb_m2_ck@190       =  /ocp/l4@4a000000/cm_core@8000/clocks/dpll_pcie_ref_m2_ck@210          4  /ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_x2_ck       ;  /ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_h11x2_ck@158        ;  /ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_h12x2_ck@15c        ;  /ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_h13x2_ck@160        ;  /ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_h14x2_ck@164        :  /ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_m2x2_ck@150         8  !/ocp/l4@4a000000/cm_core@8000/clocks/dpll_usb_clkdcoldo       3  4/ocp/l4@4a000000/cm_core@8000/clocks/func_128m_clk        3  B/ocp/l4@4a000000/cm_core@8000/clocks/func_12m_fclk        2  P/ocp/l4@4a000000/cm_core@8000/clocks/func_24m_clk         3  ]/ocp/l4@4a000000/cm_core@8000/clocks/func_48m_fclk        3  k/ocp/l4@4a000000/cm_core@8000/clocks/func_96m_fclk        9  y/ocp/l4@4a000000/cm_core@8000/clocks/l3init_60m_fclk@104          5  /ocp/l4@4a000000/cm_core@8000/clocks/clkout2_clk@6b0          ;  /ocp/l4@4a000000/cm_core@8000/clocks/l3init_960m_gfclk@6c0        C  /ocp/l4@4a000000/cm_core@8000/clocks/usb_phy1_always_on_clk32k@640        C  /ocp/l4@4a000000/cm_core@8000/clocks/usb_phy2_always_on_clk32k@688        C  /ocp/l4@4a000000/cm_core@8000/clocks/usb_phy3_always_on_clk32k@698        <  /ocp/l4@4a000000/cm_core@8000/clocks/gpu_core_gclk_mux@1220       ;  /ocp/l4@4a000000/cm_core@8000/clocks/gpu_hyd_gclk_mux@1220        =  /ocp/l4@4a000000/cm_core@8000/clocks/l3instr_ts_gclk_div@e50          8  ,/ocp/l4@4a000000/cm_core@8000/clocks/vip1_gclk_mux@1020       8  :/ocp/l4@4a000000/cm_core@8000/clocks/vip2_gclk_mux@1028       8  H/ocp/l4@4a000000/cm_core@8000/clocks/vip3_gclk_mux@1030       +  V/ocp/l4@4a000000/cm_core@8000/clockdomains        9  k/ocp/l4@4a000000/cm_core@8000/clockdomains/coreaon_clkdm          -  y/ocp/l4@4a000000/cm_core@8000/coreaon_cm@600          4  /ocp/l4@4a000000/cm_core@8000/coreaon_cm@600/clk@20       -  /ocp/l4@4a000000/cm_core@8000/l3main1_cm@700          4  /ocp/l4@4a000000/cm_core@8000/l3main1_cm@700/clk@20       *  /ocp/l4@4a000000/cm_core@8000/ipu2_cm@900         1  /ocp/l4@4a000000/cm_core@8000/ipu2_cm@900/clk@20          )  /ocp/l4@4a000000/cm_core@8000/dma_cm@a00          0  /ocp/l4@4a000000/cm_core@8000/dma_cm@a00/clk@20       *  /ocp/l4@4a000000/cm_core@8000/emif_cm@b00         1  /ocp/l4@4a000000/cm_core@8000/emif_cm@b00/clk@20          )  /ocp/l4@4a000000/cm_core@8000/atl_cm@c00          /  /ocp/l4@4a000000/cm_core@8000/atl_cm@c00/clk@0        +  /ocp/l4@4a000000/cm_core@8000/l4cfg_cm@d00        2  /ocp/l4@4a000000/cm_core@8000/l4cfg_cm@d00/clk@20         -  /ocp/l4@4a000000/cm_core@8000/l3instr_cm@e00          4  !/ocp/l4@4a000000/cm_core@8000/l3instr_cm@e00/clk@20       *  1/ocp/l4@4a000000/cm_core@8000/dss_cm@1100         1  8/ocp/l4@4a000000/cm_core@8000/dss_cm@1100/clk@20          -  D/ocp/l4@4a000000/cm_core@8000/l3init_cm@1300          4  N/ocp/l4@4a000000/cm_core@8000/l3init_cm@1300/clk@20       ,  ]/ocp/l4@4a000000/cm_core@8000/l4per_cm@1700       2  f/ocp/l4@4a000000/cm_core@8000/l4per_cm@1700/clk@0           t/ocp/l4@4ae00000            |/ocp/l4@4ae00000/counter@4000           /ocp/l4@4ae00000/prm@6000         !  /ocp/l4@4ae00000/prm@6000/clocks          0  /ocp/l4@4ae00000/prm@6000/clocks/sys_clkin1@110       :  /ocp/l4@4ae00000/prm@6000/clocks/abe_dpll_sys_clk_mux@118         =  /ocp/l4@4ae00000/prm@6000/clocks/abe_dpll_bypass_clk_mux@114          6  /ocp/l4@4ae00000/prm@6000/clocks/abe_dpll_clk_mux@10c         2  /ocp/l4@4ae00000/prm@6000/clocks/abe_24m_fclk@11c         /  /ocp/l4@4ae00000/prm@6000/clocks/aess_fclk@178        3  /ocp/l4@4ae00000/prm@6000/clocks/abe_giclk_div@174        4  /ocp/l4@4ae00000/prm@6000/clocks/abe_lp_clk_div@1d8       5  /ocp/l4@4ae00000/prm@6000/clocks/abe_sys_clk_div@120          3  #/ocp/l4@4ae00000/prm@6000/clocks/adc_gfclk_mux@1dc        7  1/ocp/l4@4ae00000/prm@6000/clocks/sys_clk1_dclk_div@1c8        7  C/ocp/l4@4ae00000/prm@6000/clocks/sys_clk2_dclk_div@1cc        9  U/ocp/l4@4ae00000/prm@6000/clocks/per_abe_x1_dclk_div@1bc          2  i/ocp/l4@4ae00000/prm@6000/clocks/dsp_gclk_div@18c         .  v/ocp/l4@4ae00000/prm@6000/clocks/gpu_dclk@1a0         7  /ocp/l4@4ae00000/prm@6000/clocks/emif_phy_dclk_div@190        8  /ocp/l4@4ae00000/prm@6000/clocks/gmac_250m_dclk_div@19c       /  /ocp/l4@4ae00000/prm@6000/clocks/gmac_main_clk        :  /ocp/l4@4ae00000/prm@6000/clocks/l3init_480m_dclk_div@1ac         6  /ocp/l4@4ae00000/prm@6000/clocks/usb_otg_dclk_div@184         3  /ocp/l4@4ae00000/prm@6000/clocks/sata_dclk_div@1c0        4  /ocp/l4@4ae00000/prm@6000/clocks/pcie2_dclk_div@1b8       3  /ocp/l4@4ae00000/prm@6000/clocks/pcie_dclk_div@1b4        2  /ocp/l4@4ae00000/prm@6000/clocks/emu_dclk_div@194         9  /ocp/l4@4ae00000/prm@6000/clocks/secure_32k_dclk_div@1c4          8  $/ocp/l4@4ae00000/prm@6000/clocks/clkoutmux0_clk_mux@158       8  7/ocp/l4@4ae00000/prm@6000/clocks/clkoutmux1_clk_mux@15c       8  J/ocp/l4@4ae00000/prm@6000/clocks/clkoutmux2_clk_mux@160       9  ]/ocp/l4@4ae00000/prm@6000/clocks/custefuse_sys_gfclk_div          -  u/ocp/l4@4ae00000/prm@6000/clocks/eve_clk@180          7  }/ocp/l4@4ae00000/prm@6000/clocks/hdmi_dpll_clk_mux@164        -  /ocp/l4@4ae00000/prm@6000/clocks/mlb_clk@134          .  /ocp/l4@4ae00000/prm@6000/clocks/mlbp_clk@130         ;  /ocp/l4@4ae00000/prm@6000/clocks/per_abe_x1_gfclk2_div@138        7  /ocp/l4@4ae00000/prm@6000/clocks/timer_sys_clk_div@144        9  /ocp/l4@4ae00000/prm@6000/clocks/video1_dpll_clk_mux@168          9  /ocp/l4@4ae00000/prm@6000/clocks/video2_dpll_clk_mux@16c          6  /ocp/l4@4ae00000/prm@6000/clocks/wkupaon_iclk_mux@108         '   /ocp/l4@4ae00000/prm@6000/clockdomains        *   /ocp/l4@4ae00000/prm@6000/wkupaon_cm@1800         1   /ocp/l4@4ae00000/prm@6000/wkupaon_cm@1800/clk@20             -/ocp/l4@4ae00000/scm_conf@c000           6/ocp/axi@0/pcie@51000000          .   ?/ocp/axi@0/pcie@51000000/interrupt-controller            J/ocp/axi@0/pcie_ep@51000000          S/ocp/axi@1/pcie@51800000          .   \/ocp/axi@1/pcie@51800000/interrupt-controller            g/ocp/ocmcram@40300000            p/ocp/ocmcram@40400000            y/ocp/ocmcram@40500000            /ocp/bandgap@4a0021e0            /ocp/dsp_system@40d00000             /ocp/padconf@4844a000         2   /ocp/padconf@4844a000/mmc1_iodelay_ddr_rev11_conf         4   /ocp/padconf@4844a000/mmc1_iodelay_ddr50_rev20_conf       5   /ocp/padconf@4844a000/mmc1_iodelay_sdr104_rev11_conf          5   /ocp/padconf@4844a000/mmc1_iodelay_sdr104_rev20_conf          4  !/ocp/padconf@4844a000/mmc2_iodelay_hs200_rev11_conf       4  !</ocp/padconf@4844a000/mmc2_iodelay_hs200_rev20_conf       7  !Z/ocp/padconf@4844a000/mmc2_iodelay_ddr_3_3v_rev11_conf        7  !{/ocp/padconf@4844a000/mmc2_iodelay_ddr_1_8v_rev11_conf        0  !/ocp/padconf@4844a000/mmc3_iodelay_manual1_conf       0  !/ocp/padconf@4844a000/mmc3_iodelay_manual1_conf       1  !/ocp/padconf@4844a000/mmc4_iodelay_ds_rev11_conf          1  !/ocp/padconf@4844a000/mmc4_iodelay_ds_rev20_conf          =  "/ocp/padconf@4844a000/mmc4_iodelay_sdr12_hs_sdr25_rev11_conf          =  "9/ocp/padconf@4844a000/mmc4_iodelay_sdr12_hs_sdr25_rev20_conf            "`/ocp/dma-controller@4a056000            "e/ocp/edma@43300000          "j/ocp/tptc@43400000          "u/ocp/tptc@43500000          "/ocp/gpio@4ae10000          "/ocp/gpio@48055000          "/ocp/gpio@48057000          "/ocp/gpio@48059000          "/ocp/gpio@4805b000          "/ocp/gpio@4805d000          "/ocp/gpio@48051000          "/ocp/gpio@48053000          "/ocp/serial@4806a000            "/ocp/serial@4806c000            "/ocp/serial@48020000            "/ocp/serial@4806e000            "/ocp/serial@48066000            "/ocp/serial@48068000            "/ocp/serial@48420000            "/ocp/serial@48422000            "/ocp/serial@48424000            "/ocp/serial@4ae2b000            "/ocp/mailbox@4a0f4000           "/ocp/mailbox@4883a000           "/ocp/mailbox@4883c000           #/ocp/mailbox@4883e000           #/ocp/mailbox@48840000         &  #/ocp/mailbox@48840000/mbox_ipu1_ipc3x         &  #*/ocp/mailbox@48840000/mbox_dsp1_ipc3x           #:/ocp/mailbox@48842000         &  #C/ocp/mailbox@48842000/mbox_ipu2_ipc3x         &  #S/ocp/mailbox@48842000/mbox_dsp2_ipc3x           #c/ocp/mailbox@48844000           #l/ocp/mailbox@48846000           #u/ocp/mailbox@4885e000           #~/ocp/mailbox@48860000           #/ocp/mailbox@48862000           #/ocp/mailbox@48864000           #/ocp/mailbox@48802000           #/ocp/timer@4ae18000         #/ocp/timer@48032000         #/ocp/timer@48034000         #/ocp/timer@48036000         #/ocp/timer@48820000         #/ocp/timer@48822000         #/ocp/timer@48824000         #/ocp/timer@48826000         #/ocp/timer@4803e000         #/ocp/timer@48086000         #/ocp/timer@48088000         #/ocp/timer@4ae20000         #/ocp/timer@48828000         $/ocp/timer@4882a000         $/ocp/timer@4882c000         $/ocp/timer@4882e000         $/ocp/wdt@4ae14000           $"/ocp/spinlock@4a0f6000          $-/ocp/ipu@58820000           $2/ocp/ipu@55020000           $7/ocp/dsp@40800000            N/ocp/i2c@48070000           $</ocp/i2c@48070000/tps659038@58        A  $F/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/smps123          @  $R/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/smps45       ?  $]/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/smps6        ?  $g/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/smps7        ?  $q/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/smps8        ?  ${/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/smps9        >  $/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/ldo1         >  $/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/ldo2         >  $/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/ldo3         >  $/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/ldo9         ?  $/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/ldoln        @  $/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/ldousb       @  $/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/regen2       @  $/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/sysen1       @  $/ocp/i2c@48070000/tps659038@58/tps659038_pmic/regulators/sysen2         $/ocp/i2c@48070000/gpio@20           $/ocp/i2c@48070000/gpio@21         #  $/ocp/i2c@48070000/tlv320aic3106@19           S/ocp/i2c@48072000           $/ocp/i2c@48072000/gpio@26         +  $/ocp/i2c@48072000/ov10633@37/port/endpoint           X/ocp/i2c@48060000            ]/ocp/i2c@4807a000           %/ocp/i2c@4807c000           %/ocp/mmc@4809c000           %/ocp/1w@480b2000            %/ocp/mmc@480b4000           %/ocp/mmc@480ad000           %#/ocp/mmc@480d1000           %(/ocp/mmu@40d01000           %2/ocp/mmu@40d02000           %</ocp/mmu@58882000           %E/ocp/mmu@55082000           %N/ocp/pruss-soc-bus@4b226004       +  %]/ocp/pruss-soc-bus@4b226004/pruss@4b200000        =  %d/ocp/pruss-soc-bus@4b226004/pruss@4b200000/memories@4b200000          8  %o/ocp/pruss-soc-bus@4b226004/pruss@4b200000/cfg@4b226000       8  %z/ocp/pruss-soc-bus@4b226004/pruss@4b200000/iep@4b22e000       ;  %/ocp/pruss-soc-bus@4b226004/pruss@4b200000/mii-rt@4b232000        I  %/ocp/pruss-soc-bus@4b226004/pruss@4b200000/interrupt-controller@4b220000          8  %/ocp/pruss-soc-bus@4b226004/pruss@4b200000/pru@4b234000       8  %/ocp/pruss-soc-bus@4b226004/pruss@4b200000/pru@4b238000       9  %/ocp/pruss-soc-bus@4b226004/pruss@4b200000/mdio@4b232400            %/ocp/pruss-soc-bus@4b2a6004       +  %/ocp/pruss-soc-bus@4b2a6004/pruss@4b280000        =  %/ocp/pruss-soc-bus@4b2a6004/pruss@4b280000/memories@4b280000          8  %/ocp/pruss-soc-bus@4b2a6004/pruss@4b280000/cfg@4b2a6000       8  %/ocp/pruss-soc-bus@4b2a6004/pruss@4b280000/iep@4b2ae000       ;  %/ocp/pruss-soc-bus@4b2a6004/pruss@4b280000/mii-rt@4b2b2000        I  %/ocp/pruss-soc-bus@4b2a6004/pruss@4b280000/interrupt-controller@4b2a0000          8  &
/ocp/pruss-soc-bus@4b2a6004/pruss@4b280000/pru@4b2b4000       8  &/ocp/pruss-soc-bus@4b2a6004/pruss@4b280000/pru@4b2b8000       9  &/ocp/pruss-soc-bus@4b2a6004/pruss@4b280000/mdio@4b2b2400            &$/ocp/regulator-abb-mpu          &,/ocp/regulator-abb-ivahd            &6/ocp/regulator-abb-dspeve           &A/ocp/regulator-abb-gpu          &I/ocp/spi@48098000           &P/ocp/spi@4809a000           &W/ocp/spi@480b8000           &^/ocp/spi@480ba000           &e/ocp/qspi@4b300000        #  &j/ocp/ocp2scp@4a090000/phy@4a096000        '  &s/ocp/ocp2scp@4a090000/pciephy@4a094000        '  &}/ocp/ocp2scp@4a090000/pciephy@4a095000          &/ocp/sata@4a141100          &/ocp/rtc@48838000         #  &/ocp/ocp2scp@4a080000/phy@4a084000        #  &/ocp/ocp2scp@4a080000/phy@4a085000        #  &/ocp/ocp2scp@4a080000/phy@4a084400          &/ocp/omap_dwc3_1@48880000         '  &/ocp/omap_dwc3_1@48880000/usb@48890000          &/ocp/omap_dwc3_2@488c0000         '  &/ocp/omap_dwc3_2@488c0000/usb@488d0000          &/ocp/omap_dwc3_3@48900000         '  &/ocp/omap_dwc3_3@48900000/usb@48910000          &/ocp/elm@48078000           &/ocp/gpmc@50000000          &/ocp/atl@4843c000           &/ocp/mcasp@48460000         &/ocp/mcasp@48464000         &/ocp/mcasp@48468000         '/ocp/mcasp@4846c000         '
/ocp/mcasp@48470000         '/ocp/mcasp@48474000         '/ocp/mcasp@48478000         '/ocp/mcasp@4847c000         '&/ocp/crossbar@4a002a48          Y/ocp/ethernet@48484000        %  '3/ocp/ethernet@48484000/mdio@48485000          &  '@/ocp/ethernet@48484000/slave@48480200         &  'K/ocp/ethernet@48484000/slave@48480300         -  'V/ocp/ethernet@48484000/cpsw-phy-sel@4a002554            '^/ocp/can@4ae3c000           'd/ocp/can@48480000           &E/ocp/gpu@56000000           'j/ocp/bb2d@59000000          'o/ocp/dss@58000000         #  $/ocp/dss@58000000/encoder@58060000        1  's/ocp/dss@58000000/encoder@58060000/port/endpoint            '|/ocp/epwmss@4843e000          "  '/ocp/epwmss@4843e000/pwm@4843e200         #  '/ocp/epwmss@4843e000/ecap@4843e100          '/ocp/epwmss@48440000          "  '/ocp/epwmss@48440000/pwm@48440200         #  '/ocp/epwmss@48440000/ecap@48440100          '/ocp/epwmss@48442000          "  '/ocp/epwmss@48442000/pwm@48442200         #  '/ocp/epwmss@48442000/ecap@48442100          '/ocp/aes@4b500000           '/ocp/aes@4b700000           '/ocp/des@480a5000           '/ocp/sham@53100000          '/ocp/rng@48090000           '/ocp/opp-supply@4a003b20            '/ocp/vip@0x48970000       !  '/ocp/vip@0x48970000/ports/port@0          ,  '/ocp/vip@0x48970000/ports/port@0/endpoint@0       !  '/ocp/vip@0x48970000/ports/port@1          !  '/ocp/vip@0x48970000/ports/port@2          !  (/ocp/vip@0x48970000/ports/port@3            (
/ocp/dsp_system@41500000            (/ocp/omap_dwc3_4@48940000         '  ("/ocp/omap_dwc3_4@48940000/usb@48950000          ('/ocp/mmu@41501000           (1/ocp/mmu@41502000           (,/ocp/dsp@41000000           (;/ocp/vip@0x48990000       !  (@/ocp/vip@0x48990000/ports/port@0          !  (F/ocp/vip@0x48990000/ports/port@1          !  (L/ocp/vip@0x48990000/ports/port@2          !  (R/ocp/vip@0x48990000/ports/port@3            (X/ocp/vip@0x489b0000       !  (]/ocp/vip@0x489b0000/ports/port@0          !  (c/ocp/vip@0x489b0000/ports/port@1            (i/thermal-zones          (w/thermal-zones/cpu_thermal        !  (/thermal-zones/cpu_thermal/trips          +  (/thermal-zones/cpu_thermal/trips/cpu_alert        *  (/thermal-zones/cpu_thermal/trips/cpu_crit         (  (/thermal-zones/cpu_thermal/cooling-maps         (/thermal-zones/gpu_thermal        *  (/thermal-zones/gpu_thermal/trips/gpu_crit           (/thermal-zones/core_thermal       ,  (/thermal-zones/core_thermal/trips/core_crit         (/thermal-zones/dspeve_thermal         0  (/thermal-zones/dspeve_thermal/trips/dspeve_crit         (/thermal-zones/iva_thermal        *  )/thermal-zones/iva_thermal/trips/iva_crit           )/extcon_usb1            )/extcon_usb2             /sound0         )&/sound0/simple-audio-card,cpu           )4/clk_ov10633_fixed          )F/fixedregulator-evm_12v0            )O/fixedregulator-evm_1v8       &  )Z/reserved-memory/ipu2-memory@95800000         &  )m/reserved-memory/dsp1-memory@99000000         &  )/reserved-memory/ipu1-memory@9d000000         &  )/reserved-memory/dsp2-memory@9f000000           )/fixedregulator-sd          )/fixedregulator-evm_3v3_sw          )/fixedregulator-aic_dvdd            )/fixedregulator-evm3v3          )/fixedregulator-evm_5v0         )/fixedregulator-evm_3v6         )/fixedregulator-mmcwl           )/fixedregulator-vtt         )/connector@1            )/connector@1/port/endpoint          */encoder@1        #  */encoder@1/ports/port@0/endpoint@0        #  *#/encoder@1/ports/port@1/endpoint@0           	#address-cells #size-cells compatible interrupt-parent model stdout-path i2c0 i2c1 i2c2 i2c3 i2c4 serial0 serial1 serial2 serial3 serial4 serial5 serial6 serial7 serial8 serial9 ethernet0 ethernet1 d_can0 d_can1 spi0 rproc0 rproc1 rproc2 rproc3 display0 sound0 sound1 interrupts interrupt-controller #interrupt-cells reg phandle device_type operating-points-v2 clocks clock-names clock-latency #cooling-cells vbb-supply vdd-supply syscon opp-shared opp-hz opp-microvolt opp-supported-hw opp-suspend ti,hwmods ranges interrupts-extended regulator-name regulator-min-microvolt regulator-max-microvolt #clock-cells ti,bit-shift #pinctrl-cells pinctrl-single,register-width pinctrl-single,function-mask pinctrl-single,pins #syscon-cells #dma-cells dma-requests ti,dma-safe-map dma-masters clock-frequency clock-mult clock-div ti,max-div ti,autoidle-shift ti,index-starts-at-one ti,invert-autoidle-bit ti,index-power-of-two assigned-clocks assigned-clock-rates assigned-clock-parents ti,dividers reg-names bus-range num-lanes linux,pci-domain phys phy-names ti,syscon-lane-sel interrupt-map-mask interrupt-map status num-ib-windows num-ob-windows ti,syscon-unaligned-access #thermal-sensor-cells pinctrl-pin-array dma-channels interrupt-names ti,tptcs gpio-controller #gpio-cells ti,no-reset-on-init ti,no-idle-on-init dmas dma-names #mbox-cells ti,mbox-num-users ti,mbox-num-fifos ti,mbox-tx ti,mbox-rx ti,timer-alwon ti,timer-secure #hwlock-cells iommus ti,rproc-standby-info mboxes timers watchdog-timers memory-region syscon-bootreg ti,palmas-override-powerhold ti,system-power-controller regulator-always-on regulator-boot-on regulator-allow-bypass lines-initial-states #sound-dai-cells adc-settle-ms ai3x-micbias-vg AVDD-supply IOVDD-supply DRVDD-supply DVDD-supply gpio-hog gpios output-low line-name mux-gpios remote-endpoint hsync-active vsync-active pclk-sample pbias-supply max-frequency mmc-ddr-1_8v mmc-ddr-3_3v vmmc-supply vqmmc-supply bus-width cd-gpios pinctrl-names pinctrl-0 pinctrl-1 pinctrl-2 pinctrl-3 pinctrl-4 pinctrl-5 pinctrl-6 pinctrl-7 pinctrl-8 sdhci-caps-mask mmc-hs200-1_8v non-removable cap-power-off-card keep-power-in-suspend #iommu-cells ti,syscon-mmuconfig ti,iommu-bus-err-back firmware-name bus_freq ti,settling-time ti,clock-cycles ti,tranxdone-status-mask ti,ldovbb-override-mask ti,ldovbb-vset-mask ti,abb_info ti,spi-num-cs syscon-chipselects spi-max-frequency spi-tx-bus-width spi-rx-bus-width label syscon-phy-power syscon-pllreset #phy-cells syscon-pcs ports-implemented phy-supply ti,sysc-mask ti,sysc-sidle utmi-mode extcon maximum-speed dr_mode snps,dis_u3_susphy_quirk snps,dis_u2_susphy_quirk snps,dis_metastability_quirk gpmc,num-cs gpmc,num-waitpins rb-gpios ti,nand-xfer-type ti,nand-ecc-opt ti,elm-id nand-bus-width gpmc,device-width gpmc,sync-clk-ps gpmc,cs-on-ns gpmc,cs-rd-off-ns gpmc,cs-wr-off-ns gpmc,adv-on-ns gpmc,adv-rd-off-ns gpmc,adv-wr-off-ns gpmc,we-on-ns gpmc,we-off-ns gpmc,oe-on-ns gpmc,oe-off-ns gpmc,access-ns gpmc,wr-access-ns gpmc,rd-cycle-ns gpmc,wr-cycle-ns gpmc,bus-turnaround-ns gpmc,cycle2cycle-delay-ns gpmc,clk-activation-ns gpmc,wr-data-mux-bus-ns ti,provided-clocks bws aws op-mode tdm-slots serial-dir tx-num-evt rx-num-evt ti,max-irqs ti,max-crossbar-sources ti,reg-size ti,irqs-reserved ti,irqs-skip ti,irqs-safe-map cpdma_channels ale_entries bd_ram_size mac_control slaves active_slave cpts_clock_mult cpts_clock_shift ti,no-idle dual_emac mac-address phy_id phy-mode dual_emac_res_vlan syscon-raminit syscon-pll-ctrl vdda_video-supply syscon-pol vdda-supply #pwm-cells ti,efuse-settings ti,absolute-max-voltage-uv slave-mode polling-delay-passive polling-delay thermal-sensors coefficients temperature hysteresis trip cooling-device id-gpio simple-audio-card,name simple-audio-card,widgets simple-audio-card,routing simple-audio-card,format simple-audio-card,bitclock-master simple-audio-card,frame-master simple-audio-card,bitclock-inversion sound-dai system-clock-frequency default-state autorepeat linux,code vin-supply reusable enable-active-high startup-delay-us ddc-i2c-bus gic wakeupgen cpu0 cpu0_opp_table l4_cfg scm scm_conf pbias_regulator pbias_mmc_reg scm_conf_clocks dss_deshdcp_clk ehrpwm0_tbclk ehrpwm1_tbclk ehrpwm2_tbclk sys_32k_ck dra7_pmx_core mmc1_pins_default mmc1_pins_sdr12 mmc1_pins_hs mmc1_pins_sdr25 mmc1_pins_sdr50 mmc1_pins_ddr50 mmc1_pins_sdr104 mmc2_pins_default mmc2_pins_hs mmc2_pins_ddr_3_3v_rev11 mmc2_pins_ddr_1_8v_rev11 mmc2_pins_ddr_rev20 mmc2_pins_hs200 mmc4_pins_default mmc4_pins_hs mmc3_pins_default mmc3_pins_hs mmc3_pins_sdr12 mmc3_pins_sdr25 mmc3_pins_sdr50 mmc4_pins_sdr12 mmc4_pins_sdr25 dcan1_pins_default dcan1_pins_sleep mcasp8_axr2_pin hdmi_i2c_pins_i2c hdmi_i2c_pins_ddc dcan2_pins_default dcan2_pins_sleep scm_conf1 scm_conf_pcie sdma_xbar edma_xbar cm_core_aon cm_core_aon_clocks atl_clkin0_ck atl_clkin1_ck atl_clkin2_ck atl_clkin3_ck hdmi_clkin_ck mlb_clkin_ck mlbp_clkin_ck pciesref_acs_clk_ck ref_clkin0_ck ref_clkin1_ck ref_clkin2_ck ref_clkin3_ck rmii_clk_ck sdvenc_clkin_ck secure_32k_clk_src_ck sys_clk32_crystal_ck sys_clk32_pseudo_ck virt_12000000_ck virt_13000000_ck virt_16800000_ck virt_19200000_ck virt_20000000_ck virt_26000000_ck virt_27000000_ck virt_38400000_ck sys_clkin2 usb_otg_clkin_ck video1_clkin_ck video1_m2_clkin_ck video2_clkin_ck video2_m2_clkin_ck dpll_abe_ck dpll_abe_x2_ck dpll_abe_m2x2_ck abe_clk dpll_abe_m2_ck dpll_abe_m3x2_ck dpll_core_byp_mux dpll_core_ck dpll_core_x2_ck dpll_core_h12x2_ck mpu_dpll_hs_clk_div dpll_mpu_ck dpll_mpu_m2_ck mpu_dclk_div dsp_dpll_hs_clk_div dpll_dsp_byp_mux dpll_dsp_ck dpll_dsp_m2_ck iva_dpll_hs_clk_div dpll_iva_byp_mux dpll_iva_ck dpll_iva_m2_ck iva_dclk dpll_gpu_byp_mux dpll_gpu_ck dpll_gpu_m2_ck dpll_core_m2_ck core_dpll_out_dclk_div dpll_ddr_byp_mux dpll_ddr_ck dpll_ddr_m2_ck dpll_gmac_byp_mux dpll_gmac_ck dpll_gmac_m2_ck video2_dclk_div video1_dclk_div hdmi_dclk_div per_dpll_hs_clk_div usb_dpll_hs_clk_div eve_dpll_hs_clk_div dpll_eve_byp_mux dpll_eve_ck dpll_eve_m2_ck eve_dclk_div dpll_core_h13x2_ck dpll_core_h14x2_ck dpll_core_h22x2_ck dpll_core_h23x2_ck dpll_core_h24x2_ck dpll_ddr_x2_ck dpll_ddr_h11x2_ck dpll_dsp_x2_ck dpll_dsp_m3x2_ck dpll_gmac_x2_ck dpll_gmac_h11x2_ck dpll_gmac_h12x2_ck dpll_gmac_h13x2_ck dpll_gmac_m3x2_ck gmii_m_clk_div hdmi_clk2_div hdmi_div_clk l3_iclk_div l4_root_clk_div video1_clk2_div video1_div_clk video2_clk2_div video2_div_clk dummy_ck cm_core_aon_clockdomains mpu_cm mpu_clkctrl dsp1_cm dsp1_clkctrl ipu1_cm ipu1_clkctrl ipu_cm ipu_clkctrl dsp2_cm dsp2_clkctrl rtc_cm rtc_clkctrl cm_core cm_core_clocks dpll_pcie_ref_ck dpll_pcie_ref_m2ldo_ck apll_pcie_in_clk_mux apll_pcie_ck optfclk_pciephy_div apll_pcie_clkvcoldo apll_pcie_clkvcoldo_div apll_pcie_m2_ck dpll_per_byp_mux dpll_per_ck dpll_per_m2_ck func_96m_aon_dclk_div dpll_usb_byp_mux dpll_usb_ck dpll_usb_m2_ck dpll_pcie_ref_m2_ck dpll_per_x2_ck dpll_per_h11x2_ck dpll_per_h12x2_ck dpll_per_h13x2_ck dpll_per_h14x2_ck dpll_per_m2x2_ck dpll_usb_clkdcoldo func_128m_clk func_12m_fclk func_24m_clk func_48m_fclk func_96m_fclk l3init_60m_fclk clkout2_clk l3init_960m_gfclk usb_phy1_always_on_clk32k usb_phy2_always_on_clk32k usb_phy3_always_on_clk32k gpu_core_gclk_mux gpu_hyd_gclk_mux l3instr_ts_gclk_div vip1_gclk_mux vip2_gclk_mux vip3_gclk_mux cm_core_clockdomains coreaon_clkdm coreaon_cm coreaon_clkctrl l3main1_cm l3main1_clkctrl ipu2_cm ipu2_clkctrl dma_cm dma_clkctrl emif_cm emif_clkctrl atl_cm atl_clkctrl l4cfg_cm l4cfg_clkctrl l3instr_cm l3instr_clkctrl dss_cm dss_clkctrl l3init_cm l3init_clkctrl l4per_cm l4per_clkctrl l4_wkup counter32k prm prm_clocks sys_clkin1 abe_dpll_sys_clk_mux abe_dpll_bypass_clk_mux abe_dpll_clk_mux abe_24m_fclk aess_fclk abe_giclk_div abe_lp_clk_div abe_sys_clk_div adc_gfclk_mux sys_clk1_dclk_div sys_clk2_dclk_div per_abe_x1_dclk_div dsp_gclk_div gpu_dclk emif_phy_dclk_div gmac_250m_dclk_div gmac_main_clk l3init_480m_dclk_div usb_otg_dclk_div sata_dclk_div pcie2_dclk_div pcie_dclk_div emu_dclk_div secure_32k_dclk_div clkoutmux0_clk_mux clkoutmux1_clk_mux clkoutmux2_clk_mux custefuse_sys_gfclk_div eve_clk hdmi_dpll_clk_mux mlb_clk mlbp_clk per_abe_x1_gfclk2_div timer_sys_clk_div video1_dpll_clk_mux video2_dpll_clk_mux wkupaon_iclk_mux prm_clockdomains wkupaon_cm wkupaon_clkctrl scm_wkup pcie1_rc pcie1_intc pcie1_ep pcie2_rc pcie2_intc ocmcram1 ocmcram2 ocmcram3 bandgap dsp1_system dra7_iodelay_core mmc1_iodelay_ddr_rev11_conf mmc1_iodelay_ddr_rev20_conf mmc1_iodelay_sdr104_rev11_conf mmc1_iodelay_sdr104_rev20_conf mmc2_iodelay_hs200_rev11_conf mmc2_iodelay_hs200_rev20_conf mmc2_iodelay_ddr_3_3v_rev11_conf mmc2_iodelay_ddr_1_8v_rev11_conf mmc3_iodelay_manual1_rev11_conf mmc3_iodelay_manual1_rev20_conf mmc4_iodelay_ds_rev11_conf mmc4_iodelay_ds_rev20_conf mmc4_iodelay_sdr12_hs_sdr25_rev11_conf mmc4_iodelay_sdr12_hs_sdr25_rev20_conf sdma edma edma_tptc0 edma_tptc1 gpio1 gpio2 gpio3 gpio4 gpio5 gpio6 gpio7 gpio8 uart1 uart2 uart3 uart4 uart5 uart6 uart7 uart8 uart9 uart10 mailbox1 mailbox2 mailbox3 mailbox4 mailbox5 mbox_ipu1_ipc3x mbox_dsp1_ipc3x mailbox6 mbox_ipu2_ipc3x mbox_dsp2_ipc3x mailbox7 mailbox8 mailbox9 mailbox10 mailbox11 mailbox12 mailbox13 timer1 timer2 timer3 timer4 timer5 timer6 timer7 timer8 timer9 timer10 timer11 timer12 timer13 timer14 timer15 timer16 wdt2 hwspinlock ipu1 ipu2 dsp1 tps659038 smps123_reg smps45_reg smps6_reg smps7_reg smps8_reg smps9_reg ldo1_reg ldo2_reg ldo3_reg ldo9_reg ldoln_reg ldousb_reg regen2 sysen1 sysen2 pcf_lcd pcf_gpio_21 tlv320aic3106 pcf_hdmi onboardLI i2c5 mmc1 hdqw1w mmc2 mmc3 mmc4 mmu0_dsp1 mmu1_dsp1 mmu_ipu1 mmu_ipu2 pruss_soc_bus1 pruss1 pruss1_mem pruss1_cfg pruss1_iep pruss1_mii_rt pruss1_intc pru1_0 pru1_1 pruss1_mdio pruss_soc_bus2 pruss2 pruss2_mem pruss2_cfg pruss2_iep pruss2_mii_rt pruss2_intc pru2_0 pru2_1 pruss2_mdio abb_mpu abb_ivahd abb_dspeve abb_gpu mcspi1 mcspi2 mcspi3 mcspi4 qspi sata_phy pcie1_phy pcie2_phy sata rtc usb2_phy1 usb2_phy2 usb3_phy1 omap_dwc3_1 usb1 omap_dwc3_2 usb2 omap_dwc3_3 usb3 elm gpmc atl mcasp1 mcasp2 mcasp3 mcasp4 mcasp5 mcasp6 mcasp7 mcasp8 crossbar_mpu davinci_mdio cpsw_emac0 cpsw_emac1 phy_sel dcan1 dcan2 bb2d dss hdmi_out epwmss0 ehrpwm0 ecap0 epwmss1 ehrpwm1 ecap1 epwmss2 ehrpwm2 ecap2 aes1 aes2 des sham rng opp_supply_mpu vip1 vin1a vin1a_ep vin2a vin1b vin2b dsp2_system omap_dwc3_4 usb4 mmu0_dsp2 mmu1_dsp2 vip2 vin3a vin4a vin3b vin4b vip3 vin5a vin6a thermal_zones cpu_thermal cpu_trips cpu_alert0 cpu_crit cpu_cooling_maps gpu_thermal gpu_crit core_thermal core_crit dspeve_thermal dspeve_crit iva_thermal iva_crit extcon_usb1 extcon_usb2 sound0_master clk_ov10633_fixed evm_12v0 evm_1v8_sw ipu2_memory_region dsp1_memory_region ipu1_memory_region dsp2_memory_region evm_3v3_sd evm_3v3_sw aic_dvdd evm_3v3 evm_5v0 evm_3v6 vmmcwl_fixed vtt_fixed hdmi0 hdmi_connector_in tpd12s015 tpd12s015_in tpd12s015_out display1 leds brightness-levels default-brightness-level enable-gpios reset-gpios data-lines touchscreen-size-x touchscreen-size-y lcd_bl tc358768_refclk dsi_bridge dsi_bridge_ports rgb_in tlc59108 backlight_led pcf_display_board touchscreen dpi_out backlight lcd_in dsi_out 