    8     (            )                                                       (   ti,dra72-evm ti,dra722 ti,dra72 ti,dra7          &            7TI DRA722 Rev C EVM    tc358768_refclk         :          1-          fixed-clock         E          backlight           :          (                (         $  (                                    (           led-backlight  =      chosen           =/ocp/serial@4806a000          aliases         (/connector 0         I/ocp/i2c@48070000            N/ocp/i2c@48072000            S/ocp/i2c@48060000            X/ocp/i2c@4807a000            ]/ocp/i2c@4807c000            b/ocp/serial@4806a000             j/ocp/serial@4806c000             r/ocp/serial@48020000             z/ocp/serial@4806e000             /ocp/serial@48066000             /ocp/serial@48068000             /ocp/serial@48420000             /ocp/serial@48422000             /ocp/serial@48424000             /ocp/serial@4ae2b000          &   /ocp/ethernet@48484000/slave@48480200         &   /ocp/ethernet@48484000/slave@48480300            /ocp/can@4ae3c000            /ocp/can@48480000            /ocp/qspi@4b300000           /ocp/ipu@58820000            /ocp/ipu@55020000            /ocp/dsp@40800000         	   /display r           /sound0       #   /ocp/dss@58000000/encoder@58060000        timer            arm,armv7-timer       0                                
           &         interrupt-controller@48211000            arm,cortex-a15-gic                   %         @  6    H!            H!              H!@             H!`                       	           &           :         interrupt-controller@48281000         &   ti,omap5-wugen-mpu ti,omap4-wugen-mpu                    %           6    H(                 &           :         cpus                                 cpu@0           Bcpu          arm,cortex-a15          6            N           b           icpu         u                                          :            opp-table            operating-points-v2-ti-cpu                     :      opp_nom-1000000000              ;          , P 0 , P 0                             opp_od-1176000000               FV          @  @ @  @                    opp_high@1500000000             Yh/          v ~  v ~                        soc          ti,omap-infra      mpu          ti,omap5-mpu            mpu          ocp          ti,dra7-l3-noc simple-bus                                                           l3_main_1 l3_main_2          6    D              E                                          
      l4@4a000000          ti,dra7-l4-cfg simple-bus                                        J    "         :      scm@2000             ti,dra7-scm-core simple-bus         6                                                             :      scm_conf@0           syscon simple-bus           6                                                           :   	   pbias_regulator@e00          ti,pbias-dra7 ti,pbias-omap         6                 	        :      pbias_mmc_omap5         pbias_mmc_omap5          w@        - 2Z        :            clocks                                    :      dss_deshdcp_clk@558         E             ti,gate-clock           b   
        R            6  X        :         ehrpwm0_tbclk@558           E             ti,gate-clock           b           R           6  X        :         ehrpwm1_tbclk@558           E             ti,gate-clock           b           R           6  X        :         ehrpwm2_tbclk@558           E             ti,gate-clock           b           R           6  X        :         sys_32k_ck          E             ti,mux-clock            b                    R           6          :   P            pinmux@1400          ti,dra7-padconf pinctrl-single          6     h                                  _           %                    n            ?        :      dcan1_pins_default                           :         dcan1_pins_sleep                            :         mmc1_pins_default         0    T     X     \     `     d     h           :         mmc1_pins_sdr12       0    T     X     \     `     d     h           :         mmc1_pins_hs          0    T     X     \     `     d     h           :         mmc1_pins_sdr25       0    T     X     \     `     d     h           :         mmc1_pins_sdr50       0    T   X   \   `   d   h         :         mmc1_pins_ddr50_rev10         0    T   X   \   `   d   h         :         mmc1_pins_ddr50_rev20         0    T    X    \    `    d    h          :         mmc1_pins_sdr104          0    T    X    \    `    d    h          :         mmc2_pins_default         P                                                            :         mmc2_pins_hs          P                                                            :         mmc2_pins_ddr_rev10       P                                                            :         mmc2_pins_ddr_rev20       P                                                  :         mmc2_pins_hs200       P                                                  :         mmc4_pins_default         0                                  :            scm_conf@1c04            syscon          6                         :         scm_conf@1c24            syscon          6  $   $        :         dma-router@b78           ti,dra7-dma-crossbar            6  x                                                        :         dma-router@c78           ti,dra7-dma-crossbar            6  x   |                                                     :         pinmux@4a002e8c          pinctrl-single          6                                       n                       :            cm_core_aon@5000             ti,dra7-cm-core-aon simple-bus                                   6  P                   P             :     clocks                                    :     atl_clkin0_ck           E             ti,dra7-atl-clock           b                  :         atl_clkin1_ck           E             ti,dra7-atl-clock           b                  :         atl_clkin2_ck           E             ti,dra7-atl-clock           b                  :         atl_clkin3_ck           E             ti,dra7-atl-clock           b                  :         hdmi_clkin_ck           E             fixed-clock                     :   0      mlb_clkin_ck            E             fixed-clock                     :         mlbp_clkin_ck           E             fixed-clock                     :         pciesref_acs_clk_ck         E             fixed-clock                  :   @      ref_clkin0_ck           E             fixed-clock                     :        ref_clkin1_ck           E             fixed-clock                     :        ref_clkin2_ck           E             fixed-clock                     :        ref_clkin3_ck           E             fixed-clock                     :        rmii_clk_ck         E             fixed-clock                     :        sdvenc_clkin_ck         E             fixed-clock                     :        secure_32k_clk_src_ck           E             fixed-clock                    :   k      sys_clk32_crystal_ck            E             fixed-clock                    :         sys_clk32_pseudo_ck         E             fixed-factor-clock          b                        b        :         virt_12000000_ck            E             fixed-clock                   :   Y      virt_13000000_ck            E             fixed-clock          ]@        :  	      virt_16800000_ck            E             fixed-clock          Y         :   [      virt_19200000_ck            E             fixed-clock         $         :   \      virt_20000000_ck            E             fixed-clock         1-         :   Z      virt_26000000_ck            E             fixed-clock                 :   ]      virt_27000000_ck            E             fixed-clock                 :   ^      virt_38400000_ck            E             fixed-clock         I         :   _      sys_clkin2          E             fixed-clock         X         :   `      usb_otg_clkin_ck            E             fixed-clock                     :   h      video1_clkin_ck         E             fixed-clock                     :   :      video1_m2_clkin_ck          E             fixed-clock                     :   /      video2_clkin_ck         E             fixed-clock                     :   ;      video2_m2_clkin_ck          E             fixed-clock                     :   .      dpll_abe_ck@1e0         E             ti,omap4-dpll-m4xen-clock           b              6                :         dpll_abe_x2_ck          E             ti,omap4-dpll-x2-clock          b           :         dpll_abe_m2x2_ck@1f0            E             ti,divider-clock            b           $           /           6           A         X        :         abe_clk@108         E             ti,divider-clock            b           $           6           o        :   b      dpll_abe_m2_ck@1f0          E             ti,divider-clock            b           $           /           6           A         X        :   d      dpll_abe_m3x2_ck@1f4            E             ti,divider-clock            b           $           /           6           A         X        :         dpll_core_byp_mux@12c           E             ti,mux-clock            b              R           6  ,        :         dpll_core_ck@120            E             ti,omap4-dpll-core-clock            b              6     $  ,  (        :         dpll_core_x2_ck         E             ti,omap4-dpll-x2-clock          b           :         dpll_core_h12x2_ck@13c          E             ti,divider-clock            b           $   ?        /           6  <         A         X        :         mpu_dpll_hs_clk_div         E             fixed-factor-clock          b                                 :         dpll_mpu_ck@160         E             ti,omap5-mpu-dpll-clock         b              6  `  d  l  h        :         dpll_mpu_m2_ck@170          E             ti,divider-clock            b           $           /           6  p         A         X        :         mpu_dclk_div            E             fixed-factor-clock          b                                 :   o      dsp_dpll_hs_clk_div         E             fixed-factor-clock          b                                 :         dpll_dsp_byp_mux@240            E             ti,mux-clock            b              R           6  @        :         dpll_dsp_ck@234         E             ti,omap4-dpll-clock         b              6  4  8  @  <                    #F         :          dpll_dsp_m2_ck@244          E             ti,divider-clock            b            $           /           6  D         A         X           !        #F         :   !      iva_dpll_hs_clk_div         E             fixed-factor-clock          b                                 :   "      dpll_iva_byp_mux@1ac            E             ti,mux-clock            b      "        R           6          :   #      dpll_iva_ck@1a0         E             ti,omap4-dpll-clock         b      #        6                   $        Ep}@        :   $      dpll_iva_m2_ck@1b0          E             ti,divider-clock            b   $        $           /           6           A         X           %        %        :   %      iva_dclk            E             fixed-factor-clock          b   %                              :   q      dpll_gpu_byp_mux@2e4            E             ti,mux-clock            b              R           6          :   &      dpll_gpu_ck@2d8         E             ti,omap4-dpll-clock         b      &        6                   '        Ly@        :   '      dpll_gpu_m2_ck@2e8          E             ti,divider-clock            b   '        $           /           6           A         X           (        _(k        :   (      dpll_core_m2_ck@130         E             ti,divider-clock            b           $           /           6  0         A         X        :   )      core_dpll_out_dclk_div          E             fixed-factor-clock          b   )                              :   s      dpll_ddr_byp_mux@21c            E             ti,mux-clock            b              R           6          :   *      dpll_ddr_ck@210         E             ti,omap4-dpll-clock         b      *        6                :   +      dpll_ddr_m2_ck@220          E             ti,divider-clock            b   +        $           /           6            A         X        :   e      dpll_gmac_byp_mux@2b4           E             ti,mux-clock            b              R           6          :   ,      dpll_gmac_ck@2a8            E             ti,omap4-dpll-clock         b      ,        6                :   -      dpll_gmac_m2_ck@2b8         E             ti,divider-clock            b   -        $           /           6           A         X        :   f      video2_dclk_div         E             fixed-factor-clock          b   .                              :   u      video1_dclk_div         E             fixed-factor-clock          b   /                              :   v      hdmi_dclk_div           E             fixed-factor-clock          b   0                              :   w      per_dpll_hs_clk_div         E             fixed-factor-clock          b                                 :   C      usb_dpll_hs_clk_div         E             fixed-factor-clock          b                                 :   G      eve_dpll_hs_clk_div         E             fixed-factor-clock          b                                 :   1      dpll_eve_byp_mux@290            E             ti,mux-clock            b      1        R           6          :   2      dpll_eve_ck@284         E             ti,omap4-dpll-clock         b      2        6                :   3      dpll_eve_m2_ck@294          E             ti,divider-clock            b   3        $           /           6           A         X        :   4      eve_dclk_div            E             fixed-factor-clock          b   4                              :         dpll_core_h13x2_ck@140          E             ti,divider-clock            b           $   ?        /           6  @         A         X        :  
      dpll_core_h14x2_ck@144          E             ti,divider-clock            b           $   ?        /           6  D         A         X        :   Q      dpll_core_h22x2_ck@154          E             ti,divider-clock            b           $   ?        /           6  T         A         X        :   =      dpll_core_h23x2_ck@158          E             ti,divider-clock            b           $   ?        /           6  X         A         X        :   V      dpll_core_h24x2_ck@15c          E             ti,divider-clock            b           $   ?        /           6  \         A         X        :        dpll_ddr_x2_ck          E             ti,omap4-dpll-x2-clock          b   +        :   5      dpll_ddr_h11x2_ck@228           E             ti,divider-clock            b   5        $   ?        /           6  (         A         X        :        dpll_dsp_x2_ck          E             ti,omap4-dpll-x2-clock          b            :   6      dpll_dsp_m3x2_ck@248            E             ti,divider-clock            b   6        $           /           6  H         A         X           7        ׄ         :   7      dpll_gmac_x2_ck         E             ti,omap4-dpll-x2-clock          b   -        :   8      dpll_gmac_h11x2_ck@2c0          E             ti,divider-clock            b   8        $   ?        /           6           A         X        :   9      dpll_gmac_h12x2_ck@2c4          E             ti,divider-clock            b   8        $   ?        /           6           A         X        :        dpll_gmac_h13x2_ck@2c8          E             ti,divider-clock            b   8        $   ?        /           6           A         X        :         dpll_gmac_m3x2_ck@2bc           E             ti,divider-clock            b   8        $           /           6           A         X        :        gmii_m_clk_div          E             fixed-factor-clock          b   9                              :        hdmi_clk2_div           E             fixed-factor-clock          b   0                              :        hdmi_div_clk            E             fixed-factor-clock          b   0                              :        l3_iclk_div@100         E             ti,divider-clock            $           R           6           b            o        :   
      l4_root_clk_div         E             fixed-factor-clock          b   
                              :         video1_clk2_div         E             fixed-factor-clock          b   :                              :        video1_div_clk          E             fixed-factor-clock          b   :                              :        video2_clk2_div         E             fixed-factor-clock          b   ;                              :        video2_div_clk          E             fixed-factor-clock          b   ;                              :        dummy_ck            E             fixed-clock                     :           clockdomains            :        mpu_cm@300           ti,omap4-cm         6                                                         :     clk@20           ti,clkctrl          6               E           :           dsp1_cm@400          ti,omap4-cm         6                                                         :     clk@20           ti,clkctrl          6               E           :           ipu1_cm@500          ti,omap4-cm         6      @                                                   :     clk@20           ti,clkctrl          6                E              <                  =        :   <         ipu_cm@540           ti,omap4-cm         6  @                                          @           :     clk@0            ti,clkctrl          6       D        E           :            dsp2_cm@600          ti,omap4-cm         6                                                         :     clk@20           ti,clkctrl          6               E           :           rtc_cm@700           ti,omap4-cm         6                                                         :      clk@40           ti,clkctrl          6   @           E           :  !            cm_core@8000             ti,dra7-cm-core simple-bus                                   6     0                  0         :  "   clocks                                    :  #   dpll_pcie_ref_ck@200            E             ti,omap4-dpll-clock         b              6                 :   >      dpll_pcie_ref_m2ldo_ck@210          E             ti,divider-clock            b   >        $           /           6           A         X        :   ?      apll_pcie_in_clk_mux@4ae06118            ti,mux-clock            b   ?   @        E            6             R           :   A      apll_pcie_ck@21c            E             ti,dra7-apll-clock          b   A   >        6             :   B      optfclk_pciephy_div@4a00821c             ti,divider-clock            b   B        E            6                        R           $           :         apll_pcie_clkvcoldo         E             fixed-factor-clock          b   B                              :  $      apll_pcie_clkvcoldo_div         E             fixed-factor-clock          b   B                              :  %      apll_pcie_m2_ck         E             fixed-factor-clock          b   B                              :   j      dpll_per_byp_mux@14c            E             ti,mux-clock            b      C        R           6  L        :   D      dpll_per_ck@140         E             ti,omap4-dpll-clock         b      D        6  @  D  L  H        :   E      dpll_per_m2_ck@150          E             ti,divider-clock            b   E        $           /           6  P         A         X        :   F      func_96m_aon_dclk_div           E             fixed-factor-clock          b   F                              :   x      dpll_usb_byp_mux@18c            E             ti,mux-clock            b      G        R           6          :   H      dpll_usb_ck@180         E             ti,omap4-dpll-j-type-clock          b      H        6                :   I      dpll_usb_m2_ck@190          E             ti,divider-clock            b   I        $           /           6           A         X        :   M      dpll_pcie_ref_m2_ck@210         E             ti,divider-clock            b   >        $           /           6           A         X        :   i      dpll_per_x2_ck          E             ti,omap4-dpll-x2-clock          b   E        :   J      dpll_per_h11x2_ck@158           E             ti,divider-clock            b   J        $   ?        /           6  X         A         X        :   K      dpll_per_h12x2_ck@15c           E             ti,divider-clock            b   J        $   ?        /           6  \         A         X        :  &      dpll_per_h13x2_ck@160           E             ti,divider-clock            b   J        $   ?        /           6  `         A         X        :  '      dpll_per_h14x2_ck@164           E             ti,divider-clock            b   J        $   ?        /           6  d         A         X        :   R      dpll_per_m2x2_ck@150            E             ti,divider-clock            b   J        $           /           6  P         A         X        :   L      dpll_usb_clkdcoldo          E             fixed-factor-clock          b   I                              :   O      func_128m_clk           E             fixed-factor-clock          b   K                              :  (      func_12m_fclk           E             fixed-factor-clock          b   L                              :  )      func_24m_clk            E             fixed-factor-clock          b   F                              :  *      func_48m_fclk           E             fixed-factor-clock          b   L                              :  +      func_96m_fclk           E             fixed-factor-clock          b   L                              :  ,      l3init_60m_fclk@104         E             ti,divider-clock            b   M        6                        :  -      clkout2_clk@6b0         E             ti,gate-clock           b   N        R           6          :  .      l3init_960m_gfclk@6c0           E             ti,gate-clock           b   O        R           6          :  /      usb_phy1_always_on_clk32k@640           E             ti,gate-clock           b   P        R           6  @        :         usb_phy2_always_on_clk32k@688           E             ti,gate-clock           b   P        R           6          :         usb_phy3_always_on_clk32k@698           E             ti,gate-clock           b   P        R           6          :         gpu_core_gclk_mux@1220          E             ti,mux-clock            b   Q   R   (        R           6              S           (        :   S      gpu_hyd_gclk_mux@1220           E             ti,mux-clock            b   Q   R   (        R           6              T           (        :   T      l3instr_ts_gclk_div@e50         E             ti,divider-clock            b   U        R           6  P                          :  0      vip1_gclk_mux@1020          E             ti,mux-clock            b   
   V        R           6           :  1      vip2_gclk_mux@1028          E             ti,mux-clock            b   
   V        R           6  (        :  2      vip3_gclk_mux@1030          E             ti,mux-clock            b   
   V        R           6  0        :  3         clockdomains            :  4   coreaon_clkdm            ti,clockdomain          b   I        :  5         coreaon_cm@600           ti,omap4-cm         6                                                         :  6   clk@20           ti,clkctrl          6               E           :            l3main1_cm@700           ti,omap4-cm         6                                                         :  7   clk@20           ti,clkctrl          6       t        E           :  8         ipu2_cm@900          ti,omap4-cm         6  	                                           	            :  9   clk@20           ti,clkctrl          6               E           :  :         dma_cm@a00           ti,omap4-cm         6  
                                           
            :  ;   clk@20           ti,clkctrl          6               E           :  <         emif_cm@b00          ti,omap4-cm         6                                                         :  =   clk@20           ti,clkctrl          6               E           :  >         atl_cm@c00           ti,omap4-cm         6                                                         :  ?   clk@0            ti,clkctrl          6               E           :            l4cfg_cm@d00             ti,omap4-cm         6                                                         :  @   clk@20           ti,clkctrl          6               E           :  A         l3instr_cm@e00           ti,omap4-cm         6                                                         :  B   clk@20           ti,clkctrl          6               E           :  C         dss_cm@1100          ti,omap4-cm         6                                                         :  D   clk@20           ti,clkctrl          6               E           :            l3init_cm@1300           ti,omap4-cm         6                                                         :  E   clk@20           ti,clkctrl          6               E           :            l4per_cm@1700            ti,omap4-cm         6                                                         :  F   clk@0            ti,clkctrl          6              E              W  h              X        :   W               l4@4ae00000          ti,dra7-l4-wkup simple-bus                                       J            :  G   counter@4000             ti,omap-counter32k          6  @    @        counter_32k         :  H      prm@6000             ti,dra7-prm simple-bus          6  `   0                                                          `   0         :  I   clocks                                    :  J   sys_clkin1@110          E             ti,mux-clock            b   Y   Z   [   \   ]   ^   _        6           A        :         abe_dpll_sys_clk_mux@118            E             ti,mux-clock            b      `        6          :   a      abe_dpll_bypass_clk_mux@114         E             ti,mux-clock            b   a   P        6          :         abe_dpll_clk_mux@10c            E             ti,mux-clock            b   a   P        6          :         abe_24m_fclk@11c            E             ti,divider-clock            b           6                        :   X      aess_fclk@178           E             ti,divider-clock            b   b        6  x        $           :   c      abe_giclk_div@174           E             ti,divider-clock            b   c        6  t        $           :  K      abe_lp_clk_div@1d8          E             ti,divider-clock            b           6                         :         abe_sys_clk_div@120         E             ti,divider-clock            b           6           $           :  L      adc_gfclk_mux@1dc           E             ti,mux-clock            b      `   P        6          :  M      sys_clk1_dclk_div@1c8           E             ti,divider-clock            b           $   @        6           o        :   l      sys_clk2_dclk_div@1cc           E             ti,divider-clock            b   `        $   @        6           o        :   m      per_abe_x1_dclk_div@1bc         E             ti,divider-clock            b   d        $   @        6           o        :   n      dsp_gclk_div@18c            E             ti,divider-clock            b   !        $   @        6           o        :   p      gpu_dclk@1a0            E             ti,divider-clock            b   (        $   @        6           o        :   r      emif_phy_dclk_div@190           E             ti,divider-clock            b   e        $   @        6           o        :   t      gmac_250m_dclk_div@19c          E             ti,divider-clock            b   f        $   @        6           o        :   g      gmac_main_clk           E             fixed-factor-clock          b   g                              :         l3init_480m_dclk_div@1ac            E             ti,divider-clock            b   M        $   @        6           o        :   y      usb_otg_dclk_div@184            E             ti,divider-clock            b   h        $   @        6           o        :   z      sata_dclk_div@1c0           E             ti,divider-clock            b           $   @        6           o        :   {      pcie2_dclk_div@1b8          E             ti,divider-clock            b   i        $   @        6           o        :   |      pcie_dclk_div@1b4           E             ti,divider-clock            b   j        $   @        6           o        :   }      emu_dclk_div@194            E             ti,divider-clock            b           $   @        6           o        :   ~      secure_32k_dclk_div@1c4         E             ti,divider-clock            b   k        $   @        6           o        :         clkoutmux0_clk_mux@158          E             ti,mux-clock          X  b   l   m   n   o   p   q   r   s   t   g   u   v   w   x   y   z   {   |   }   ~              6  X        :  N      clkoutmux1_clk_mux@15c          E             ti,mux-clock          X  b   l   m   n   o   p   q   r   s   t   g   u   v   w   x   y   z   {   |   }   ~              6  \        :  O      clkoutmux2_clk_mux@160          E             ti,mux-clock          X  b   l   m   n   o   p   q   r   s   t   g   u   v   w   x   y   z   {   |   }   ~              6  `        :   N      custefuse_sys_gfclk_div         E             fixed-factor-clock          b                                 :  P      eve_clk@180         E             ti,mux-clock            b   4   7        6          :  Q      hdmi_dpll_clk_mux@164           E             ti,mux-clock            b      `        6  d        :  R      mlb_clk@134         E             ti,divider-clock            b           $   @        6  4         o        :  S      mlbp_clk@130            E             ti,divider-clock            b           $   @        6  0         o        :  T      per_abe_x1_gfclk2_div@138           E             ti,divider-clock            b   d        $   @        6  8         o        :  U      timer_sys_clk_div@144           E             ti,divider-clock            b           6  D        $           :  V      video1_dpll_clk_mux@168         E             ti,mux-clock            b      `        6  h        :  W      video2_dpll_clk_mux@16c         E             ti,mux-clock            b      `        6  l        :  X      wkupaon_iclk_mux@108            E             ti,mux-clock            b              6          :   U         clockdomains            :  Y      wkupaon_cm@1800          ti,omap4-cm         6                                                         :  Z   clk@20           ti,clkctrl          6       l        E           :               scm_conf@c000            syscon          6              :            axi@0            simple-bus                                   Q   Q     0               pcie@51000000           6Q       Q     L               rc_dbics ti_conf config                                                              Bpci       0               0                0  0                             %                                  pcie1                    
  pcie-phy0                                              `  1                                                                                            ?okay             ti,dra726-pcie-rc ti,dra7-pcie          :  [   interrupt-controller                                   %           :            pcie_ep@51000000             6Q      (Q     LQ     (            &  ep_dbics ti_conf ep_dbics2 addr_space                                        F           U           pcie1                    
  pcie-phy0           d                             	  ?disabled          "   ti,dra726-pcie-ep ti,dra7-pcie-ep           :  \         axi@1            simple-bus                                   Q  Q    0     0            	  ?disabled       pcie@51800000           6Q      Q    L               rc_dbics ti_conf config               c         d                                    Bpci       0               0               00  0                             %                                 pcie2                    
  pcie-phy0                                `  1                                                                                             ti,dra726-pcie-rc ti,dra7-pcie          :  ]   interrupt-controller                                   %           :               ocmcram@40300000          
   mmio-sram           6@0                 @0                                      :  ^   sram-hs@0            ti,secure-ram           6                 ocmcram@40400000          	  ?disabled          
   mmio-sram           6@@                 @@                                      :  _      ocmcram@40500000          	  ?disabled          
   mmio-sram           6@P                 @P                                      :  `      bandgap@4a0021e0          0  6J !   J #,   J #   ,J #   <J %d   J %t   P         ti,dra752-bandgap                  y                      :         dsp_system@40d00000          syscon          6@             :         padconf@4844a000             ti,dra7-iodelay         6HD                                     _           :  a   mmc1_iodelay_ddr50_conf             L      $        0  _      <        H        T                 ,          8   8      D   L      P   [      \   c      (          4          @          L          X                :         mmc1_iodelay_sdr104_rev10_conf               0  m  ,          8         D          P   /      \         (   }      4   +      @        L        X  _            :  b      mmc1_iodelay_sdr104_rev20_conf                 @  ,          8   (      D   S      P   b      \   j      (   3      4          @  k      L         X              :         mmc2_iodelay_ddr_conf        \                 w                           ~                                            `                               N                 
                             +                 h                                                                                          d                :         mmc2_iodelay_hs200_rev10_conf                   _              }         d        f                                          h                                   8        m                O        J      d              :  c      mmc2_iodelay_hs200_rev20_conf                                     x         F      h                         F                 h       x                        '         [                            e                d  h            :            dma-controller@4a056000          ti,omap4430-sdma            6J`          0                             	          
                                             dma_system          :         edma@43300000            ti,edma3-tpcc           tpcc            6C0           	  edma3_cc          $        i         h         g         '  edma3_ccint edma3_mperr edma3_ccerrint             @                                        :         tptc@43400000            ti,edma3-tptc           tptc0           6C@                   r           edma3_tcerrint          :         tptc@43500000            ti,edma3-tptc           tptc1           6CP                   s           edma3_tcerrint          :         gpio@4ae10000            ti,omap4-gpio           6J                               gpio1                                        %           :  d      gpio@48055000            ti,omap4-gpio           6HP                              gpio2                                        %           :  e      gpio@48057000            ti,omap4-gpio           6Hp                              gpio3                                        %           :         gpio@48059000            ti,omap4-gpio           6H                              gpio4                                        %           :  f      gpio@4805b000            ti,omap4-gpio           6H                              gpio5                                        %           :         gpio@4805d000            ti,omap4-gpio           6H                              gpio6                                        %           :         gpio@48051000            ti,omap4-gpio           6H                              gpio7                                        %           :         gpio@48053000            ti,omap4-gpio           6H0                   t           gpio8                                        %           :  g      serial@4806a000          ti,dra742-uart ti,omap4-uart            6H                      C                uart1           l         ?okay                  1      2        tx rx           :  h      serial@4806c000          ti,dra742-uart ti,omap4-uart            6H                   D           uart2           l       	  ?disabled                  3      4        tx rx           :  i      serial@48020000          ti,dra742-uart ti,omap4-uart            6H                    E           uart3           l       	  ?disabled                  5      6        tx rx           :  j      serial@4806e000          ti,dra742-uart ti,omap4-uart            6H                   A           uart4           l       	  ?disabled                  7      8        tx rx           :  k      serial@48066000          ti,dra742-uart ti,omap4-uart            6H`                   d           uart5           l       	  ?disabled                  ?      @        tx rx           :  l      serial@48068000          ti,dra742-uart ti,omap4-uart            6H                   e           uart6           l       	  ?disabled                  O      P        tx rx           :  m      serial@48420000          ti,dra742-uart ti,omap4-uart            6HB                               uart7           l       	  ?disabled            :  n      serial@48422000          ti,dra742-uart ti,omap4-uart            6HB                               uart8           l       	  ?disabled            :  o      serial@48424000          ti,dra742-uart ti,omap4-uart            6HB@                              uart9           l       	  ?disabled            :  p      serial@4ae2b000          ti,dra742-uart ti,omap4-uart            6J                              uart10          l       	  ?disabled            :  q      mailbox@4a0f4000             ti,omap4-mailbox            6J@          $                                      	  mailbox1                                           	  ?disabled            :  r      mailbox@4883a000             ti,omap4-mailbox            6H          0                                                	  mailbox2                                           	  ?disabled            :  s      mailbox@4883c000             ti,omap4-mailbox            6H          0                                                	  mailbox3                                           	  ?disabled            :  t      mailbox@4883e000             ti,omap4-mailbox            6H          0                                                	  mailbox4                                           	  ?disabled            :  u      mailbox@48840000             ti,omap4-mailbox            6H           0                                                	  mailbox5                                             ?okay            :      mbox_ipu1_ipc3x         (                 3                 ?okay            :         mbox_dsp1_ipc3x         (                 3                 ?okay            :            mailbox@48842000             ti,omap4-mailbox            6H           0                                                	  mailbox6                                             ?okay            :      mbox_ipu2_ipc3x         (                 3                 ?okay            :            mailbox@48844000             ti,omap4-mailbox            6H@          0                                            	  mailbox7                                           	  ?disabled            :  v      mailbox@48846000             ti,omap4-mailbox            6H`          0                                            	  mailbox8                                           	  ?disabled            :  w      mailbox@4885e000             ti,omap4-mailbox            6H          0        	         
                           	  mailbox9                                           	  ?disabled            :  x      mailbox@48860000             ti,omap4-mailbox            6H           0                                            
  mailbox10                                          	  ?disabled            :  y      mailbox@48862000             ti,omap4-mailbox            6H           0                                            
  mailbox11                                          	  ?disabled            :  z      mailbox@48864000             ti,omap4-mailbox            6H@          0                                            
  mailbox12                                          	  ?disabled            :  {      mailbox@48802000             ti,omap4-mailbox            6H           0        {         |         }         ~         
  mailbox13                                          	  ?disabled            :  |      timer@4ae18000           ti,omap5430-timer           6J                               timer1           >        ifck         b                  :  }      timer@48032000           ti,omap5430-timer           6H                    !           timer2          b   W   8           ifck         :  ~      timer@48034000           ti,omap5430-timer           6H@                   "           timer3          b   W   @           ifck         :         timer@48036000           ti,omap5430-timer           6H`                   #           timer4          b   W   H           ifck         :         timer@48820000           ti,omap5430-timer           6H                    $           timer5          b                 ifck         :         timer@48822000           ti,omap5430-timer           6H                    %           timer6          b                  ifck         :        timer@48824000           ti,omap5430-timer           6H@                   &           timer7          b      (           ifck         :         timer@48826000           ti,omap5430-timer           6H`                   '           timer8          b      0           ifck         :         timer@4803e000           ti,omap5430-timer           6H                   (           timer9          b   W   P           ifck         :         timer@48086000           ti,omap5430-timer           6H`                   )           timer10         b   W   (           ifck         :         timer@48088000           ti,omap5430-timer           6H                   *           timer11         b   W   0           ifck         :         timer@4ae20000           ti,omap5430-timer           6J                    Z           timer12          >         M        b      (           ifck         :        timer@48828000           ti,omap5430-timer           6H                  S           timer13         b   W              ifck         :        timer@4882a000           ti,omap5430-timer           6H                  T           timer14         b   W              ifck         :        timer@4882c000           ti,omap5430-timer           6H                  U           timer15         b   W              ifck         :        timer@4882e000           ti,omap5430-timer           6H                  V           timer16         b   W  0           ifck         :        wdt@4ae14000             ti,omap3-wdt            6J@                   K         
  wd_timer2           :        spinlock@4a0f6000            ti,omap4-hwspinlock         6J`          	  spinlock            ]           :        dmm@4e000000             ti,omap5-dmm            6N                     l           dmm       ipu@58820000             ti,dra7-ipu         6X             l2ram           ipu1            k           rJ U         ?okay                                                              :        ipu@55020000             ti,dra7-ipu         6U             l2ram           ipu2            k           rJ          ?okay                                                              :        dsp@40800000             ti,dra7-dsp         6@    @     @             l2ram l1pram l1dram         dsp1               	  \        k              rJ T         ?okay                                                           :        i2c@48070000             ti,omap4-i2c            6H                    3                                     i2c1            ?okay                     :     edt-ft5506@38                          &  d        :           )          )	          (                 6   8         edt,edt-ft5506 edt,edt-ft5x06          ?okay         gpio@27         :                              6   '         nxp,pcf8575       tlc59116@40         :          6   @         ti,tlc59108                              bl@2            :          6         
  	backlight e          tc358768@0e         :          (                 irefclk         b                                    6            toshiba,tc358768 xp,   display         :          )          	lcd         6             osd,osd101t2587-53ts      port       endpoint            :                        ports           :                               port@1          6      endpoint            :                     port@0          6       endpoint            :          (                            gpio@20          nxp,pcf8575         6                                         %            &                         :        gpio@21          ti,pcf8575 nxp,pcf8575          6   !                                               %            &                         :         tlv320aic3106@19                         ti,tlv320aic3106            6              (                   ?okay                                              -           :         tps65917@58         6   X                            ti,tps65917                  %            9        :      tps65917_pmic            ti,tps65917-pmic            T           d           t                                                                                   regulators          :     smps1           smps1            P        -                           :         smps2           smps2            P        - 0                          :        smps3           smps3            P        -                           :        smps4           smps4            w@        - w@                          :         smps5           smps5            p        - p                          :        ldo1            ldo1             w@        - 2Z                                   :         ldo2            ldo2             w@        - w@                                   :         ldo3            ldo3             w@        - w@                          :        ldo5            ldo5             w@        - w@                          :         ldo4            ldo4             2Z        - 2Z                 :               tps65917_power_button            ti,palmas-pwrbutton          &                           ,        :               i2c@48072000             ti,omap4-i2c            6H                    4                                     i2c2          	  ?disabled            :        i2c@48060000             ti,omap4-i2c            6H                    8                                     i2c3          	  ?disabled            :        i2c@4807a000             ti,omap4-i2c            6H                   9                                     i2c4          	  ?disabled            :        i2c@4807c000             ti,omap4-i2c            6H                   7                                     i2c5            ?okay                     :     pcf8575@26           ti,pcf8575 nxp,pcf8575          6   &                              +        :      p1           W        `                f        qvin6_sel_s0          ov10633@37           ovti,ov10633            6   7        b           ixvclk           {                      port       endpoint                                                         :               tca6416@20          ?okay             ti,tca6416          6                                :         ov490@24             ovti,ov490          6   $      0  {                                          port       endpoint@0                                                     :                  mmc@4809c000             ti,dra7-sdhci           6H	                   N           mmc1            ?okay                       q                         *  default hs sdr12 sdr25 sdr50 ddr50 sdr104                                 +           5                 >           K           U           _           i           s              }              :        1w@480b2000          ti,omap3-1w         6H                    5           hdq1w           :        mmc@480b4000             ti,dra7-sdhci           6H@                   Q           mmc2            ?okay            q                                                   default hs ddr_1_8v hs200_1_8v                     +                    K           U              _                         :        mmc@480ad000             ti,dra7-sdhci           6H
                   Y           mmc3          	  ?disabled            А              @          :        mmc@480d1000             ti,dra7-sdhci           6H                   [           mmc4            ?okay            q              @                     >           +                                      default hs sdr12 sdr25                     K           U           _                                     :     wifi@2        
   ti,wl1835           6            &                          mmu@40d01000             ti,dra7-dsp-iommu           6@                            
  mmu0_dsp1                                      :         mmu@40d02000             ti,dra7-dsp-iommu           6@                             
  mmu1_dsp1                                     :         mmu@58882000             ti,dra7-iommu           6X                            	  mmu_ipu1                                 :         mmu@55082000             ti,dra7-iommu           6U                            	  mmu_ipu2                                 :         pruss-soc-bus@4b226004           ti,am5728-pruss-soc-bus         6K"`           pruss1                                          	  ?disabled            :     pruss@4b200000           ti,am5728-pruss         6K            `                                                                                        0  host2 host3 host4 host5 host6 host7 host8 host9                                         	  ?disabled            :     memories@4b200000           6K       K       K!             dram0 dram1 shrdram2            :        cfg@4b226000             syscon          6K"`             :        iep@4b22e000             syscon          6K"           :        mii-rt@4b232000          syscon          6K#     X        :        interrupt-controller@4b220000            ti,am5728-pruss-intc            6K"                       %           :         pru@4b234000             ti,am5728-pru           6K#@   0 K"     K"$            iram control debug          	am57xx-pru1_0-fw             &                         vring kick          :        pru@4b238000             ti,am5728-pru           6K#   0 K"@    K"D            iram control debug          	am57xx-pru1_1-fw             &                         vring kick          :        mdio@4b232400            ti,davinci_mdio         6K#$                                      b           ifck         	" B@      	  ?disabled            :              pruss-soc-bus@4b2a6004           ti,am5728-pruss-soc-bus         6K*`           pruss2                                          	  ?disabled            :     pruss@4b280000           ti,am5728-pruss         6K(           `                                                                                        0  host2 host3 host4 host5 host6 host7 host8 host9                                         	  ?disabled            :     memories@4b280000           6K(      K(      K)             dram0 dram1 shrdram2            :        cfg@4b2a6000             syscon          6K*`             :        iep@4b2ae000             syscon          6K*           :        mii-rt@4b2b2000          syscon          6K+     X        :        interrupt-controller@4b2a0000            ti,am5728-pruss-intc            6K*                       %           :         pru@4b2b4000             ti,am5728-pru           6K+@   0 K*     K*$            iram control debug          	am57xx-pru2_0-fw             &                         vring kick          :        pru@4b2b8000             ti,am5728-pru           6K+   0 K*@    K*D            iram control debug          	am57xx-pru2_1-fw             &                         vring kick          :        mdio@4b2b2400            ti,davinci_mdio         6K+$                                      b           ifck         	" B@      	  ?disabled            :              regulator-abb-mpu         
   ti,abb-v3           abb_mpu                                    b           	+   2        	<         (  6J}   J}   J`   J ;    JX         D  setup-address control-address int-address efuse-address ldo-address         	L           	e           	}         H  	 ,                  @                 v                        :         regulator-abb-ivahd       
   ti,abb-v3         
  abb_ivahd                                      b           	+   2        	<         (  6J~4   J~$   J`   J %   J $p         D  setup-address control-address int-address efuse-address ldo-address         	L@           	e           	}         H  	                   0                                         :        regulator-abb-dspeve          
   ti,abb-v3           abb_dspeve                                     b           	+   2        	<         (  6J~0   J~    J`   J %   J $l         D  setup-address control-address int-address efuse-address ldo-address         	L            	e           	}         H  	                   0                                         :        regulator-abb-gpu         
   ti,abb-v3           abb_gpu                                    b           	+   2        	<         (  6J}   J}   J`   J ;   JT         D  setup-address control-address int-address efuse-address ldo-address         	L           	e           	}         H  	                   v                                          :        spi@48098000             ti,omap4-mcspi          6H	                   <                                     mcspi1          	         @        #      $      %      &      '      (      )      *         tx0 rx0 tx1 rx1 tx2 rx2 tx3 rx3       	  ?disabled            :        spi@4809a000             ti,omap4-mcspi          6H	                   =                                     mcspi2          	                  +      ,      -      .        tx0 rx0 tx1 rx1       	  ?disabled            :        spi@480b8000             ti,omap4-mcspi          6H                   V                                     mcspi3          	                               tx0 rx0       	  ?disabled            :        spi@480ba000             ti,omap4-mcspi          6H                   +                                     mcspi4          	                 F      G        tx0 rx0       	  ?disabled            :        qspi@4b300000            ti,dra7xxx-qspi         6K0     \              qspi_base qspi_mmap         	   	  X                                  qspi            b   W  8           ifck         	                 W           ?okay            	         :     m25p80@0             s25fl256s1          	         6            	           	                               partition@0       	  	QSPI.SPL            6             partition@1         	QSPI.SPL.backup1            6            partition@2         	QSPI.SPL.backup2            6            partition@3         	QSPI.SPL.backup3            6            partition@4         	QSPI.u-boot         6            partition@5         	QSPI.u-boot-spl-os          6            partition@6         	QSPI.u-boot-env         6            partition@7         	QSPI.u-boot-env.backup1         6            partition@8         	QSPI.kernel         6            partition@9         	QSPI.file-system            6   b              ocp2scp@4a090000             ti,omap-ocp2scp                                           6J	            	  ocp2scp3       phy@4a096000             ti,phy-pipe3-sata           6J	`    J	d    dJ	h    @        phy_rx phy_tx pll_ctrl          	   	  t        b         h           isysclk refclk           
	   	          
            :         pciephy@4a094000             ti,phy-pipe3-pcie           6J	@    J	D    d        phy_rx phy_tx           	              
$            4  b   >   ?                  	         
            ;  idpll_ref dpll_ref_m2 wkupclk refclk div-clk phy-div sysclk          
            :         pciephy@4a095000             ti,phy-pipe3-pcie           6J	P    J	T    d        phy_rx phy_tx           	               
$            4  b   >   ?                  	         
            ;  idpll_ref dpll_ref_m2 wkupclk refclk div-clk phy-div sysclk          
          	  ?disabled            :            sata@4a141100            snps,dwc-ahci           6J     J                   1                    	  sata-phy            b      h           sata            
/           :        rtc@48838000             ti,am3352-rtc           6H                                        rtcss           b   P        :        ocp2scp@4a080000             ti,omap-ocp2scp                                           6J            	  ocp2scp1       phy@4a084000             ti,dra7x-usb2 ti,omap-usb2          6J@            	   	           b                    iwkupclk refclk          
            
A           :         phy@4a085000              ti,dra7x-usb2-phy2 ti,omap-usb2         6JP            	   	  t        b                     iwkupclk refclk          
            
A           :         phy@4a084400             ti,omap-usb3            6JD    JH    dJL    @        phy_rx phy_tx pll_ctrl          	   	  p        b                       iwkupclk sysclk refclk           
            :            target-module@4a0dd000           ti,sysc-omap4-sr ti,sysc            smartreflex_core            6J8           sysc            
L           
Y                     b                  ifck                                      J          target-module@4a0d9000           ti,sysc-omap4-sr ti,sysc            smartreflex_mpu         6J8           sysc            
L           
Y                     b                  ifck                                      J          omap_dwc3_1@48880000             ti,dwc3         usb_otg_ss1         6H                    H                                    
g                    
q           :     usb@48890000          
   snps,dwc3           6H   p       $         G          G          H           peripheral host otg                       usb2-phy usb3-phy           
xsuper-speed         
otg          
         
        
q           :           omap_dwc3_2@488c0000             ti,dwc3         usb_otg_ss2         6H                    W                                    
g                    
q           :     usb@488d0000          
   snps,dwc3           6H   p       $         I          I          W           peripheral host otg                  	  usb2-phy            
xhigh-speed          
host             
         
         
        
q           :           omap_dwc3_3@48900000             ti,dwc3         usb_otg_ss3         6H                   X                                    
g                  	  ?disabled            :     usb@48910000          
   snps,dwc3           6H   p       $         X          X         X           peripheral host otg         
xhigh-speed          
otg          
         
        :           elm@48078000             ti,am3352-elm           6H                             elm         ?okay            :         gpmc@50000000            ti,am3352-gpmc          gpmc            6P     |                                            rxtx            
           
                                             %                             	  ?disabled                                  :      nand@0,0             ti,omap2-nand           6                    &                                  
                   prefetch-dma            bch8            &           0           ?           Q            b            p   P           P                       <           <           
           2                      (           (           P        $   P        5   P        F            ]            w                                            partition@0       	  	NAND.SPL            6             partition@1         	NAND.SPL.backup1            6            partition@2         	NAND.SPL.backup2            6            partition@3         	NAND.SPL.backup3            6            partition@4         	NAND.u-boot-spl-os          6            partition@5         	NAND.u-boot         6            partition@6         	NAND.u-boot-env         6            partition@7         	NAND.u-boot-env.backup1         6            partition@8         	NAND.kernel         6             partition@9         	NAND.file-system            6   `              atl@4843c000             ti,dra7-atl         6HC           atl                             b                  ifck         ?okay               a                              `   d                
@   V"         :     atl2                                   mcasp@48460000           ti,dra7-mcasp-audio         mcasp1          6HF      E             mpu dat                h          g           tx rx                                     tx rx         $  b                                   ifck ahclkx ahclkr         	  ?disabled            :        mcasp@48464000           ti,dra7-mcasp-audio         mcasp2          6HF@     E             mpu dat                                     tx rx                                     tx rx         $  b   W  `      W  `      W  `           ifck ahclkx ahclkr         	  ?disabled            :        mcasp@48468000           ti,dra7-mcasp-audio         mcasp3          6HF     F              mpu dat                                     tx rx                                     tx rx           b   W  h      W  h           ifck ahclkx          ?okay                           W  h                                                                                           :         mcasp@4846c000           ti,dra7-mcasp-audio         mcasp4          6HF     HC`            mpu dat                                     tx rx                                     tx rx           b   W        W             ifck ahclkx        	  ?disabled            :        mcasp@48470000           ti,dra7-mcasp-audio         mcasp5          6HG      HC            mpu dat                                     tx rx                                     tx rx           b   W  x      W  x           ifck ahclkx        	  ?disabled            :        mcasp@48474000           ti,dra7-mcasp-audio         mcasp6          6HG@     HD            mpu dat                                     tx rx                                     tx rx           b   W        W             ifck ahclkx        	  ?disabled            :        mcasp@48478000           ti,dra7-mcasp-audio         mcasp7          6HG     HE             mpu dat                                     tx rx                                     tx rx           b   W        W             ifck ahclkx        	  ?disabled            :        mcasp@4847c000           ti,dra7-mcasp-audio         mcasp8          6HG     HE@            mpu dat                                     tx rx                                     tx rx           b   W        W             ifck ahclkx        	  ?disabled            :        crossbar@4a002a48            ti,irq-crossbar         6J *H  0                  &           %                                             $                                 5   
                 B            :         ethernet@48484000            ti,dra7-cpsw ti,cpsw            gmac            b                  	  ifck cpts            S           b           n            z                                   xL                   6HH@    HHR   .                                         0        N         O         P         Q                       	        ?okay          $                 	         
                    :     mdio@48485000            ti,cpsw-mdio ti,davinci_mdio                                      davinci_mdio            	" B@        6HHP            :      ethernet-phy@2          6                                                       &                          +        :        ethernet-phy@3          6                                                       &                          +        :           slave@48480200          I                U            	  \rgmii-id            e           :        slave@48480300          I                U            	  \rgmii-id            e           :        cpsw-phy-sel@4a002554            ti,dra7xx-cpsw-phy-sel          6J %T         	  gmii-sel            :           can@4ae3c000             ti,dra7-d_can           dcan1           6J             x   	  X                              b      h           ?ok          default sleep active                       K           U           :        can@48480000             ti,dra7-d_can           dcan2           6HH              x   	  X                             b         	  ?disabled            :        gpu@56000000             ti,dra7-sgx544 img,sgx544           6V              gpu_ocp_base                              gpu         b   
   S   T        iiclk fclk1 fclk2            ?ok          :        bb2d@59000000            ti,dra7-bb2d            6Y                     x           bb2d            b                  ifck         ?okay            :        dss@58000000             ti,dra7-dss         ?ok        	  dss_core               	  8                                          6X      X @T   X C             dss pll1_clkctrl pll1           b                            ifck video1_clk                     :     ports                                port@0          6       endpoint            :          (                         dispc@58001000           ti,dra7-dispc           6X                             
  dss_dispc           b                  ifck            	  4      encoder@58060000             ti,dra7-hdmi             6X     X    X    X            wp pll phy core                `           ?ok        	  dss_hdmi            b          	          
        ifck sys_clk               L      	  audio_tx                       :     port       endpoint                       :                  epwmss@4843e000           ti,dra746-pwmss ti,am33xx-pwmss         6HC    0        epwmss0                                	  ?disabled                     :     pwm@4843e200          "   ti,dra746-ehrpwm ti,am3352-ehrpwm                      6HC            b            
  itbclk fck         	  ?disabled            :        ecap@4843e100            ti,dra746-ecap ti,am3352-ecap                      6HC            b           ifck       	  ?disabled            :           epwmss@48440000           ti,dra746-pwmss ti,am33xx-pwmss         6HD     0        epwmss1                                	  ?disabled                     :     pwm@48440200          "   ti,dra746-ehrpwm ti,am3352-ehrpwm                      6HD            b            
  itbclk fck         	  ?disabled            :        ecap@48440100            ti,dra746-ecap ti,am3352-ecap                      6HD            b           ifck       	  ?disabled            :           epwmss@48442000           ti,dra746-pwmss ti,am33xx-pwmss         6HD     0        epwmss2                                	  ?disabled                     :     pwm@48442200          "   ti,dra746-ehrpwm ti,am3352-ehrpwm                      6HD"            b            
  itbclk fck         	  ?disabled            :        ecap@48442100            ti,dra746-ecap ti,am3352-ecap                      6HD!            b           ifck       	  ?disabled            :           aes@4b500000             ti,omap4-aes            aes1            6KP                    P                 o          n            tx rx           b   
        ifck         :        aes@4b700000             ti,omap4-aes            aes2            6Kp                    ;                 r          q            tx rx           b   
        ifck         :        des@480a5000             ti,omap4-des            des         6H
P                   M                 u      t        tx rx           b   
        ifck         :        sham@53100000            ti,omap5-sham           sham            6K                   .                 w            rx          b   
        ifck         :        rng@48090000             ti,omap4-rng            rng         6H	                     /           b   
        ifck         :        opp-supply@4a003b20          ti,omap5-opp-supply         6J ;             ,     @    v            `        :        vpe          ti,vpe          vpe         b   V        ifck          6H     H    HW    H            vpe_top sc csc vpdma                  b                                   vip@0x48970000           ti,vip1       @  6H    HU    HW    HX    HZ    H\    H]    H          ,  vip parser0 csc0 sc0 parser1 csc1 sc1 vpdma         vip1                  _                       	  4                                  ?okay            :     ports                                port@0          6            :        port@1          6           :     endpoint@0                              :            port@2          6           :        port@3          6           :              cal@4845b000             ti,dra72-cal            cal         6HE    HE    @HE    @      "  cal_top cal_rx_core0 cal_rx_core1                  w              	                                    ?okay            :     ports                                port@0          6            :     endpoint@0                              :            port@1          6           :                 thermal-zones           :     cpu_thermal                    (          6               F              :     trips           :     cpu_alert           S         _          Ipassive         :         cpu_crit            S         _        	  Icritical            :           cooling-maps            :     map0            j           o               gpu_thermal                    (          6              F              :     trips      gpu_crit            S         _        	  Icritical            :              core_thermal                       (          6              F              :     trips      core_crit           S         _        	  Icritical            :              dspeve_thermal                     (          6              F              :     trips      dspeve_crit         S         _        	  Icritical            :              iva_thermal                    (          6              F              :     trips      iva_crit            S         _        	  Icritical            :                 pmu          arm,cortex-a15-pmu           &                           fixedregulator-evm12v0           regulator-fixed       	  evm_12v0                      -                            :         fixedregulator-evm5v0            regulator-fixed         evm_5v0          LK@        - LK@        ~                             :         fixedregulator-evm_3v6           regulator-fixed         evm_3v6          6        - 6        ~                             :         fixedregulator-vsys3v3           regulator-fixed       	  vsys_3v3             2Z        - 2Z        ~                             :         fixedregulator-evm_3v3           regulator-fixed         evm_3v3          2Z        - 2Z        ~                             :         fixedregulator-aic_dvdd          regulator-fixed       	  aic_dvdd            ~            w@        - w@        :         fixedregulator-sd            regulator-fixed         evm_3v3_sd           2Z        - 2Z        ~                                      :         extcon_usb1          linux,extcon-usb-gpio                             :         extcon_usb2          linux,extcon-usb-gpio                             :         connector            hdmi-connector          	hdmi            Ia           :     port       endpoint                       :               encoder          ti,tpd12s015          $  `                                      :     ports                                port@0          6       endpoint                       :            port@1          6      endpoint                       :                  sound0           simple-audio-card           DRA7xx-EVM        H  Headphone Headphone Jack Line Line Out Microphone Mic Jack Line Line In         Headphone Jack HPLOUT Headphone Jack HPROUT Line Out LLOUT Line Out RLOUT MIC3L Mic Jack MIC3R Mic Jack Mic Jack Mic Bias LINE1L Line In LINE1R Line In         dsp_b                      /            N        :     simple-audio-card,cpu           s           } V"         :         simple-audio-card,codec         s           b            clk_ov10633_fixed           E             fixed-clock         n6         :         fixedregulator-mmcwl             regulator-fixed         vmmcwl_fixed             w@        - w@                                   :         memory@0            Bmemory          6                    reserved-memory                                      ipu2_cma@95800000            shared-dma-pool         6                             ?okay            :         dsp1_cma@99000000            shared-dma-pool         6                               ?okay            :         ipu1_cma@9d000000            shared-dma-pool         6                               ?okay            :            fixedregulator-evm_1v8           regulator-fixed         evm_1v8          w@        - w@        ~                             :         __symbols__       5  )/ocp/i2c@48070000/tc358768@0e/ports/port@1/endpoint  ocp      5  )/ocp/i2c@48070000/tc358768@0e/display/port/endpoint  ocp      '  #/ocp/i2c@48070000/tc358768@0e/display         )  )/ocp/dss@58000000/ports/port@0/endpoint          !  )/ocp/i2c@48070000/edt-ft5506@38    $        )/ocp/i2c@48070000/gpio@27  4      $  )r/ocp/i2c@48070000/tlc59116@40/bl@2          )i/ocp/i2c@48070000/tlc59116@40  o      5  )b/ocp/i2c@48070000/tc358768@0e/ports/port@0/endpoint  ocp      %  )Q/ocp/i2c@48070000/tc358768@0e/ports            )F/ocp/i2c@48070000/tc358768@0e  /        )6/tc358768_refclk           )//backlight          /interrupt-controller@48211000          /interrupt-controller@48281000          /cpus/cpu@0         /opp-table          /ocp/l4@4a000000            /ocp/l4@4a000000/scm@2000         %  /ocp/l4@4a000000/scm@2000/scm_conf@0          9  /ocp/l4@4a000000/scm@2000/scm_conf@0/pbias_regulator@e00          I  /ocp/l4@4a000000/scm@2000/scm_conf@0/pbias_regulator@e00/pbias_mmc_omap5          ,  /ocp/l4@4a000000/scm@2000/scm_conf@0/clocks       @  /ocp/l4@4a000000/scm@2000/scm_conf@0/clocks/dss_deshdcp_clk@558       >  /ocp/l4@4a000000/scm@2000/scm_conf@0/clocks/ehrpwm0_tbclk@558         >  /ocp/l4@4a000000/scm@2000/scm_conf@0/clocks/ehrpwm1_tbclk@558         >  -/ocp/l4@4a000000/scm@2000/scm_conf@0/clocks/ehrpwm2_tbclk@558         7  ;/ocp/l4@4a000000/scm@2000/scm_conf@0/clocks/sys_32k_ck        &  F/ocp/l4@4a000000/scm@2000/pinmux@1400         9  T/ocp/l4@4a000000/scm@2000/pinmux@1400/dcan1_pins_default          7  g/ocp/l4@4a000000/scm@2000/pinmux@1400/dcan1_pins_sleep        8  x/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc1_pins_default       6  /ocp/l4@4a000000/scm@2000/pinmux@1400/mmc1_pins_sdr12         3  /ocp/l4@4a000000/scm@2000/pinmux@1400/mmc1_pins_hs        6  /ocp/l4@4a000000/scm@2000/pinmux@1400/mmc1_pins_sdr25         6  /ocp/l4@4a000000/scm@2000/pinmux@1400/mmc1_pins_sdr50         <  /ocp/l4@4a000000/scm@2000/pinmux@1400/mmc1_pins_ddr50_rev10       <  /ocp/l4@4a000000/scm@2000/pinmux@1400/mmc1_pins_ddr50_rev20       7  /ocp/l4@4a000000/scm@2000/pinmux@1400/mmc1_pins_sdr104        8  /ocp/l4@4a000000/scm@2000/pinmux@1400/mmc2_pins_default       3  /ocp/l4@4a000000/scm@2000/pinmux@1400/mmc2_pins_hs        :  #/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc2_pins_ddr_rev10         :  7/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc2_pins_ddr_rev20         6  K/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc2_pins_hs200         8  [/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc4_pins_default       (  m/ocp/l4@4a000000/scm@2000/scm_conf@1c04       (  w/ocp/l4@4a000000/scm@2000/scm_conf@1c24       )  /ocp/l4@4a000000/scm@2000/dma-router@b78          )  /ocp/l4@4a000000/scm@2000/dma-router@c78          *  /ocp/l4@4a000000/scm@2000/pinmux@4a002e8c         "  /ocp/l4@4a000000/cm_core_aon@5000         )  /ocp/l4@4a000000/cm_core_aon@5000/clocks          7  /ocp/l4@4a000000/cm_core_aon@5000/clocks/atl_clkin0_ck        7  /ocp/l4@4a000000/cm_core_aon@5000/clocks/atl_clkin1_ck        7  /ocp/l4@4a000000/cm_core_aon@5000/clocks/atl_clkin2_ck        7  /ocp/l4@4a000000/cm_core_aon@5000/clocks/atl_clkin3_ck        7  /ocp/l4@4a000000/cm_core_aon@5000/clocks/hdmi_clkin_ck        6  /ocp/l4@4a000000/cm_core_aon@5000/clocks/mlb_clkin_ck         7  /ocp/l4@4a000000/cm_core_aon@5000/clocks/mlbp_clkin_ck        =  '/ocp/l4@4a000000/cm_core_aon@5000/clocks/pciesref_acs_clk_ck          7  ;/ocp/l4@4a000000/cm_core_aon@5000/clocks/ref_clkin0_ck        7  I/ocp/l4@4a000000/cm_core_aon@5000/clocks/ref_clkin1_ck        7  W/ocp/l4@4a000000/cm_core_aon@5000/clocks/ref_clkin2_ck        7  e/ocp/l4@4a000000/cm_core_aon@5000/clocks/ref_clkin3_ck        5  s/ocp/l4@4a000000/cm_core_aon@5000/clocks/rmii_clk_ck          9  /ocp/l4@4a000000/cm_core_aon@5000/clocks/sdvenc_clkin_ck          ?  /ocp/l4@4a000000/cm_core_aon@5000/clocks/secure_32k_clk_src_ck        >  /ocp/l4@4a000000/cm_core_aon@5000/clocks/sys_clk32_crystal_ck         =  /ocp/l4@4a000000/cm_core_aon@5000/clocks/sys_clk32_pseudo_ck          :  /ocp/l4@4a000000/cm_core_aon@5000/clocks/virt_12000000_ck         :  /ocp/l4@4a000000/cm_core_aon@5000/clocks/virt_13000000_ck         :  /ocp/l4@4a000000/cm_core_aon@5000/clocks/virt_16800000_ck         :  /ocp/l4@4a000000/cm_core_aon@5000/clocks/virt_19200000_ck         :  /ocp/l4@4a000000/cm_core_aon@5000/clocks/virt_20000000_ck         :  #/ocp/l4@4a000000/cm_core_aon@5000/clocks/virt_26000000_ck         :  4/ocp/l4@4a000000/cm_core_aon@5000/clocks/virt_27000000_ck         :  E/ocp/l4@4a000000/cm_core_aon@5000/clocks/virt_38400000_ck         4  V/ocp/l4@4a000000/cm_core_aon@5000/clocks/sys_clkin2       :  a/ocp/l4@4a000000/cm_core_aon@5000/clocks/usb_otg_clkin_ck         9  r/ocp/l4@4a000000/cm_core_aon@5000/clocks/video1_clkin_ck          <  /ocp/l4@4a000000/cm_core_aon@5000/clocks/video1_m2_clkin_ck       9  /ocp/l4@4a000000/cm_core_aon@5000/clocks/video2_clkin_ck          <  /ocp/l4@4a000000/cm_core_aon@5000/clocks/video2_m2_clkin_ck       9  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_abe_ck@1e0          8  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_abe_x2_ck       >  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_abe_m2x2_ck@1f0         5  /ocp/l4@4a000000/cm_core_aon@5000/clocks/abe_clk@108          <  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_abe_m2_ck@1f0       >  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_abe_m3x2_ck@1f4         ?  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_byp_mux@12c        :  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_ck@120         9  +/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_x2_ck          @  ;/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_h12x2_ck@13c       =  N/ocp/l4@4a000000/cm_core_aon@5000/clocks/mpu_dpll_hs_clk_div          9  b/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_mpu_ck@160          <  n/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_mpu_m2_ck@170       6  }/ocp/l4@4a000000/cm_core_aon@5000/clocks/mpu_dclk_div         =  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dsp_dpll_hs_clk_div          >  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_dsp_byp_mux@240         9  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_dsp_ck@234          <  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_dsp_m2_ck@244       =  /ocp/l4@4a000000/cm_core_aon@5000/clocks/iva_dpll_hs_clk_div          >  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_iva_byp_mux@1ac         9  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_iva_ck@1a0          <  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_iva_m2_ck@1b0       2  
/ocp/l4@4a000000/cm_core_aon@5000/clocks/iva_dclk         >  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gpu_byp_mux@2e4         9  $/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gpu_ck@2d8          <  0/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gpu_m2_ck@2e8       =  ?/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_m2_ck@130          @  O/ocp/l4@4a000000/cm_core_aon@5000/clocks/core_dpll_out_dclk_div       >  f/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_ddr_byp_mux@21c         9  w/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_ddr_ck@210          <  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_ddr_m2_ck@220       ?  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gmac_byp_mux@2b4        :  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gmac_ck@2a8         =  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gmac_m2_ck@2b8          9  /ocp/l4@4a000000/cm_core_aon@5000/clocks/video2_dclk_div          9  /ocp/l4@4a000000/cm_core_aon@5000/clocks/video1_dclk_div          7  /ocp/l4@4a000000/cm_core_aon@5000/clocks/hdmi_dclk_div        =  /ocp/l4@4a000000/cm_core_aon@5000/clocks/per_dpll_hs_clk_div          =  /ocp/l4@4a000000/cm_core_aon@5000/clocks/usb_dpll_hs_clk_div          =  /ocp/l4@4a000000/cm_core_aon@5000/clocks/eve_dpll_hs_clk_div          >  +/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_eve_byp_mux@290         9  </ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_eve_ck@284          <  H/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_eve_m2_ck@294       6  W/ocp/l4@4a000000/cm_core_aon@5000/clocks/eve_dclk_div         @  d/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_h13x2_ck@140       @  w/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_h14x2_ck@144       @  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_h22x2_ck@154       @  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_h23x2_ck@158       @  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_h24x2_ck@15c       8  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_ddr_x2_ck       ?  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_ddr_h11x2_ck@228        8  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_dsp_x2_ck       >  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_dsp_m3x2_ck@248         9  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gmac_x2_ck          @  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gmac_h11x2_ck@2c0       @  '/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gmac_h12x2_ck@2c4       @  :/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gmac_h13x2_ck@2c8       ?  M/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gmac_m3x2_ck@2bc        8  _/ocp/l4@4a000000/cm_core_aon@5000/clocks/gmii_m_clk_div       7  n/ocp/l4@4a000000/cm_core_aon@5000/clocks/hdmi_clk2_div        6  |/ocp/l4@4a000000/cm_core_aon@5000/clocks/hdmi_div_clk         9  /ocp/l4@4a000000/cm_core_aon@5000/clocks/l3_iclk_div@100          9  /ocp/l4@4a000000/cm_core_aon@5000/clocks/l4_root_clk_div          9  /ocp/l4@4a000000/cm_core_aon@5000/clocks/video1_clk2_div          8  /ocp/l4@4a000000/cm_core_aon@5000/clocks/video1_div_clk       9  /ocp/l4@4a000000/cm_core_aon@5000/clocks/video2_clk2_div          8  /ocp/l4@4a000000/cm_core_aon@5000/clocks/video2_div_clk       2  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dummy_ck         /  /ocp/l4@4a000000/cm_core_aon@5000/clockdomains        -  /ocp/l4@4a000000/cm_core_aon@5000/mpu_cm@300          4  /ocp/l4@4a000000/cm_core_aon@5000/mpu_cm@300/clk@20       .  /ocp/l4@4a000000/cm_core_aon@5000/dsp1_cm@400         5   /ocp/l4@4a000000/cm_core_aon@5000/dsp1_cm@400/clk@20          .  -/ocp/l4@4a000000/cm_core_aon@5000/ipu1_cm@500         5  5/ocp/l4@4a000000/cm_core_aon@5000/ipu1_cm@500/clk@20          -  B/ocp/l4@4a000000/cm_core_aon@5000/ipu_cm@540          3  I/ocp/l4@4a000000/cm_core_aon@5000/ipu_cm@540/clk@0        .  U/ocp/l4@4a000000/cm_core_aon@5000/dsp2_cm@600         5  ]/ocp/l4@4a000000/cm_core_aon@5000/dsp2_cm@600/clk@20          -  j/ocp/l4@4a000000/cm_core_aon@5000/rtc_cm@700          4  q/ocp/l4@4a000000/cm_core_aon@5000/rtc_cm@700/clk@40         }/ocp/l4@4a000000/cm_core@8000         %  /ocp/l4@4a000000/cm_core@8000/clocks          :  /ocp/l4@4a000000/cm_core@8000/clocks/dpll_pcie_ref_ck@200         @  /ocp/l4@4a000000/cm_core@8000/clocks/dpll_pcie_ref_m2ldo_ck@210       C  /ocp/l4@4a000000/cm_core@8000/clocks/apll_pcie_in_clk_mux@4ae06118        6  /ocp/l4@4a000000/cm_core@8000/clocks/apll_pcie_ck@21c         B  /ocp/l4@4a000000/cm_core@8000/clocks/optfclk_pciephy_div@4a00821c         9  /ocp/l4@4a000000/cm_core@8000/clocks/apll_pcie_clkvcoldo          =  /ocp/l4@4a000000/cm_core@8000/clocks/apll_pcie_clkvcoldo_div          5  /ocp/l4@4a000000/cm_core@8000/clocks/apll_pcie_m2_ck          :  ./ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_byp_mux@14c         5  ?/ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_ck@140          8  K/ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_m2_ck@150       ;  Z/ocp/l4@4a000000/cm_core@8000/clocks/func_96m_aon_dclk_div        :  p/ocp/l4@4a000000/cm_core@8000/clocks/dpll_usb_byp_mux@18c         5  /ocp/l4@4a000000/cm_core@8000/clocks/dpll_usb_ck@180          8  /ocp/l4@4a000000/cm_core@8000/clocks/dpll_usb_m2_ck@190       =  /ocp/l4@4a000000/cm_core@8000/clocks/dpll_pcie_ref_m2_ck@210          4  /ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_x2_ck       ;  /ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_h11x2_ck@158        ;  /ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_h12x2_ck@15c        ;  /ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_h13x2_ck@160        ;  /ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_h14x2_ck@164        :  /ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_m2x2_ck@150         8  /ocp/l4@4a000000/cm_core@8000/clocks/dpll_usb_clkdcoldo       3  +/ocp/l4@4a000000/cm_core@8000/clocks/func_128m_clk        3  9/ocp/l4@4a000000/cm_core@8000/clocks/func_12m_fclk        2  G/ocp/l4@4a000000/cm_core@8000/clocks/func_24m_clk         3  T/ocp/l4@4a000000/cm_core@8000/clocks/func_48m_fclk        3  b/ocp/l4@4a000000/cm_core@8000/clocks/func_96m_fclk        9  p/ocp/l4@4a000000/cm_core@8000/clocks/l3init_60m_fclk@104          5  /ocp/l4@4a000000/cm_core@8000/clocks/clkout2_clk@6b0          ;  /ocp/l4@4a000000/cm_core@8000/clocks/l3init_960m_gfclk@6c0        C  /ocp/l4@4a000000/cm_core@8000/clocks/usb_phy1_always_on_clk32k@640        C  /ocp/l4@4a000000/cm_core@8000/clocks/usb_phy2_always_on_clk32k@688        C  /ocp/l4@4a000000/cm_core@8000/clocks/usb_phy3_always_on_clk32k@698        <  /ocp/l4@4a000000/cm_core@8000/clocks/gpu_core_gclk_mux@1220       ;  /ocp/l4@4a000000/cm_core@8000/clocks/gpu_hyd_gclk_mux@1220        =  /ocp/l4@4a000000/cm_core@8000/clocks/l3instr_ts_gclk_div@e50          8  #/ocp/l4@4a000000/cm_core@8000/clocks/vip1_gclk_mux@1020       8  1/ocp/l4@4a000000/cm_core@8000/clocks/vip2_gclk_mux@1028       8  ?/ocp/l4@4a000000/cm_core@8000/clocks/vip3_gclk_mux@1030       +  M/ocp/l4@4a000000/cm_core@8000/clockdomains        9  b/ocp/l4@4a000000/cm_core@8000/clockdomains/coreaon_clkdm          -  p/ocp/l4@4a000000/cm_core@8000/coreaon_cm@600          4  {/ocp/l4@4a000000/cm_core@8000/coreaon_cm@600/clk@20       -  /ocp/l4@4a000000/cm_core@8000/l3main1_cm@700          4  /ocp/l4@4a000000/cm_core@8000/l3main1_cm@700/clk@20       *  /ocp/l4@4a000000/cm_core@8000/ipu2_cm@900         1  /ocp/l4@4a000000/cm_core@8000/ipu2_cm@900/clk@20          )  /ocp/l4@4a000000/cm_core@8000/dma_cm@a00          0  /ocp/l4@4a000000/cm_core@8000/dma_cm@a00/clk@20       *  /ocp/l4@4a000000/cm_core@8000/emif_cm@b00         1  /ocp/l4@4a000000/cm_core@8000/emif_cm@b00/clk@20          )  /ocp/l4@4a000000/cm_core@8000/atl_cm@c00          /  /ocp/l4@4a000000/cm_core@8000/atl_cm@c00/clk@0        +  /ocp/l4@4a000000/cm_core@8000/l4cfg_cm@d00        2  /ocp/l4@4a000000/cm_core@8000/l4cfg_cm@d00/clk@20         -  /ocp/l4@4a000000/cm_core@8000/l3instr_cm@e00          4  /ocp/l4@4a000000/cm_core@8000/l3instr_cm@e00/clk@20       *  (/ocp/l4@4a000000/cm_core@8000/dss_cm@1100         1  //ocp/l4@4a000000/cm_core@8000/dss_cm@1100/clk@20          -  ;/ocp/l4@4a000000/cm_core@8000/l3init_cm@1300          4  E/ocp/l4@4a000000/cm_core@8000/l3init_cm@1300/clk@20       ,  T/ocp/l4@4a000000/cm_core@8000/l4per_cm@1700       2  ]/ocp/l4@4a000000/cm_core@8000/l4per_cm@1700/clk@0           k/ocp/l4@4ae00000            s/ocp/l4@4ae00000/counter@4000           ~/ocp/l4@4ae00000/prm@6000         !  /ocp/l4@4ae00000/prm@6000/clocks          0  /ocp/l4@4ae00000/prm@6000/clocks/sys_clkin1@110       :  /ocp/l4@4ae00000/prm@6000/clocks/abe_dpll_sys_clk_mux@118         =  /ocp/l4@4ae00000/prm@6000/clocks/abe_dpll_bypass_clk_mux@114          6  /ocp/l4@4ae00000/prm@6000/clocks/abe_dpll_clk_mux@10c         2  /ocp/l4@4ae00000/prm@6000/clocks/abe_24m_fclk@11c         /  /ocp/l4@4ae00000/prm@6000/clocks/aess_fclk@178        3  /ocp/l4@4ae00000/prm@6000/clocks/abe_giclk_div@174        4  /ocp/l4@4ae00000/prm@6000/clocks/abe_lp_clk_div@1d8       5  
/ocp/l4@4ae00000/prm@6000/clocks/abe_sys_clk_div@120          3  /ocp/l4@4ae00000/prm@6000/clocks/adc_gfclk_mux@1dc        7  (/ocp/l4@4ae00000/prm@6000/clocks/sys_clk1_dclk_div@1c8        7  :/ocp/l4@4ae00000/prm@6000/clocks/sys_clk2_dclk_div@1cc        9  L/ocp/l4@4ae00000/prm@6000/clocks/per_abe_x1_dclk_div@1bc          2  `/ocp/l4@4ae00000/prm@6000/clocks/dsp_gclk_div@18c         .  m/ocp/l4@4ae00000/prm@6000/clocks/gpu_dclk@1a0         7  v/ocp/l4@4ae00000/prm@6000/clocks/emif_phy_dclk_div@190        8  /ocp/l4@4ae00000/prm@6000/clocks/gmac_250m_dclk_div@19c       /  /ocp/l4@4ae00000/prm@6000/clocks/gmac_main_clk        :  /ocp/l4@4ae00000/prm@6000/clocks/l3init_480m_dclk_div@1ac         6  /ocp/l4@4ae00000/prm@6000/clocks/usb_otg_dclk_div@184         3  /ocp/l4@4ae00000/prm@6000/clocks/sata_dclk_div@1c0        4  /ocp/l4@4ae00000/prm@6000/clocks/pcie2_dclk_div@1b8       3  /ocp/l4@4ae00000/prm@6000/clocks/pcie_dclk_div@1b4        2  /ocp/l4@4ae00000/prm@6000/clocks/emu_dclk_div@194         9  /ocp/l4@4ae00000/prm@6000/clocks/secure_32k_dclk_div@1c4          8  /ocp/l4@4ae00000/prm@6000/clocks/clkoutmux0_clk_mux@158       8  ./ocp/l4@4ae00000/prm@6000/clocks/clkoutmux1_clk_mux@15c       8  A/ocp/l4@4ae00000/prm@6000/clocks/clkoutmux2_clk_mux@160       9  T/ocp/l4@4ae00000/prm@6000/clocks/custefuse_sys_gfclk_div          -  l/ocp/l4@4ae00000/prm@6000/clocks/eve_clk@180          7  t/ocp/l4@4ae00000/prm@6000/clocks/hdmi_dpll_clk_mux@164        -  /ocp/l4@4ae00000/prm@6000/clocks/mlb_clk@134          .  /ocp/l4@4ae00000/prm@6000/clocks/mlbp_clk@130         ;  /ocp/l4@4ae00000/prm@6000/clocks/per_abe_x1_gfclk2_div@138        7  /ocp/l4@4ae00000/prm@6000/clocks/timer_sys_clk_div@144        9  /ocp/l4@4ae00000/prm@6000/clocks/video1_dpll_clk_mux@168          9  /ocp/l4@4ae00000/prm@6000/clocks/video2_dpll_clk_mux@16c          6  /ocp/l4@4ae00000/prm@6000/clocks/wkupaon_iclk_mux@108         '  /ocp/l4@4ae00000/prm@6000/clockdomains        *   	/ocp/l4@4ae00000/prm@6000/wkupaon_cm@1800         1   /ocp/l4@4ae00000/prm@6000/wkupaon_cm@1800/clk@20             $/ocp/l4@4ae00000/scm_conf@c000           -/ocp/axi@0/pcie@51000000          .   6/ocp/axi@0/pcie@51000000/interrupt-controller            A/ocp/axi@0/pcie_ep@51000000          J/ocp/axi@1/pcie@51800000          .   S/ocp/axi@1/pcie@51800000/interrupt-controller            ^/ocp/ocmcram@40300000            g/ocp/ocmcram@40400000            p/ocp/ocmcram@40500000            y/ocp/bandgap@4a0021e0            /ocp/dsp_system@40d00000             /ocp/padconf@4844a000         .   /ocp/padconf@4844a000/mmc1_iodelay_ddr50_conf         5   /ocp/padconf@4844a000/mmc1_iodelay_sdr104_rev10_conf          5   /ocp/padconf@4844a000/mmc1_iodelay_sdr104_rev20_conf          ,   /ocp/padconf@4844a000/mmc2_iodelay_ddr_conf       4  !/ocp/padconf@4844a000/mmc2_iodelay_hs200_rev10_conf       4  !)/ocp/padconf@4844a000/mmc2_iodelay_hs200_rev20_conf         !G/ocp/dma-controller@4a056000            !L/ocp/edma@43300000          !Q/ocp/tptc@43400000          !\/ocp/tptc@43500000          !g/ocp/gpio@4ae10000          !m/ocp/gpio@48055000          !s/ocp/gpio@48057000          !y/ocp/gpio@48059000          !/ocp/gpio@4805b000          !/ocp/gpio@4805d000          !/ocp/gpio@48051000          !/ocp/gpio@48053000          !/ocp/serial@4806a000            !/ocp/serial@4806c000            !/ocp/serial@48020000            !/ocp/serial@4806e000            !/ocp/serial@48066000            !/ocp/serial@48068000            !/ocp/serial@48420000            !/ocp/serial@48422000            !/ocp/serial@48424000            !/ocp/serial@4ae2b000            !/ocp/mailbox@4a0f4000           !/ocp/mailbox@4883a000           !/ocp/mailbox@4883c000           !/ocp/mailbox@4883e000           !/ocp/mailbox@48840000         &  "/ocp/mailbox@48840000/mbox_ipu1_ipc3x         &  "/ocp/mailbox@48840000/mbox_dsp1_ipc3x           "!/ocp/mailbox@48842000         &  "*/ocp/mailbox@48842000/mbox_ipu2_ipc3x           ":/ocp/mailbox@48844000           "C/ocp/mailbox@48846000           "L/ocp/mailbox@4885e000           "U/ocp/mailbox@48860000           "_/ocp/mailbox@48862000           "i/ocp/mailbox@48864000           "s/ocp/mailbox@48802000           "}/ocp/timer@4ae18000         "/ocp/timer@48032000         "/ocp/timer@48034000         "/ocp/timer@48036000         "/ocp/timer@48820000         "/ocp/timer@48822000         "/ocp/timer@48824000         "/ocp/timer@48826000         "/ocp/timer@4803e000         "/ocp/timer@48086000         "/ocp/timer@48088000         "/ocp/timer@4ae20000         "/ocp/timer@48828000         "/ocp/timer@4882a000         "/ocp/timer@4882c000         "/ocp/timer@4882e000         "/ocp/wdt@4ae14000           "/ocp/spinlock@4a0f6000          #/ocp/ipu@58820000           #	/ocp/ipu@55020000           #/ocp/dsp@40800000            N/ocp/i2c@48070000           #/ocp/i2c@48070000/gpio@20           #/ocp/i2c@48070000/gpio@21         #  #'/ocp/i2c@48070000/tlv320aic3106@19          #5/ocp/i2c@48070000/tps65917@58         7  #>/ocp/i2c@48070000/tps65917@58/tps65917_pmic/regulators        =  #R/ocp/i2c@48070000/tps65917@58/tps65917_pmic/regulators/smps1          =  #\/ocp/i2c@48070000/tps65917@58/tps65917_pmic/regulators/smps2          =  #f/ocp/i2c@48070000/tps65917@58/tps65917_pmic/regulators/smps3          =  #p/ocp/i2c@48070000/tps65917@58/tps65917_pmic/regulators/smps4          =  #z/ocp/i2c@48070000/tps65917@58/tps65917_pmic/regulators/smps5          <  #/ocp/i2c@48070000/tps65917@58/tps65917_pmic/regulators/ldo1       <  #/ocp/i2c@48070000/tps65917@58/tps65917_pmic/regulators/ldo2       <  #/ocp/i2c@48070000/tps65917@58/tps65917_pmic/regulators/ldo3       <  #/ocp/i2c@48070000/tps65917@58/tps65917_pmic/regulators/ldo5       <  #/ocp/i2c@48070000/tps65917@58/tps65917_pmic/regulators/ldo4          S/ocp/i2c@48072000            X/ocp/i2c@48060000            ]/ocp/i2c@4807a000           #/ocp/i2c@4807c000           #/ocp/i2c@4807c000/pcf8575@26          +  #/ocp/i2c@4807c000/ov10633@37/port/endpoint          #/ocp/i2c@4807c000/tca6416@20          +  #/ocp/i2c@4807c000/ov490@24/port/endpoint@0          #/ocp/mmc@4809c000           #/ocp/1w@480b2000            #/ocp/mmc@480b4000           #/ocp/mmc@480ad000           #/ocp/mmc@480d1000           #/ocp/mmu@40d01000           $/ocp/mmu@40d02000           $/ocp/mmu@58882000           $/ocp/mmu@55082000           $#/ocp/pruss-soc-bus@4b226004       +  $2/ocp/pruss-soc-bus@4b226004/pruss@4b200000        =  $9/ocp/pruss-soc-bus@4b226004/pruss@4b200000/memories@4b200000          8  $D/ocp/pruss-soc-bus@4b226004/pruss@4b200000/cfg@4b226000       8  $O/ocp/pruss-soc-bus@4b226004/pruss@4b200000/iep@4b22e000       ;  $Z/ocp/pruss-soc-bus@4b226004/pruss@4b200000/mii-rt@4b232000        I  $h/ocp/pruss-soc-bus@4b226004/pruss@4b200000/interrupt-controller@4b220000          8  $t/ocp/pruss-soc-bus@4b226004/pruss@4b200000/pru@4b234000       8  ${/ocp/pruss-soc-bus@4b226004/pruss@4b200000/pru@4b238000       9  $/ocp/pruss-soc-bus@4b226004/pruss@4b200000/mdio@4b232400            $/ocp/pruss-soc-bus@4b2a6004       +  $/ocp/pruss-soc-bus@4b2a6004/pruss@4b280000        =  $/ocp/pruss-soc-bus@4b2a6004/pruss@4b280000/memories@4b280000          8  $/ocp/pruss-soc-bus@4b2a6004/pruss@4b280000/cfg@4b2a6000       8  $/ocp/pruss-soc-bus@4b2a6004/pruss@4b280000/iep@4b2ae000       ;  $/ocp/pruss-soc-bus@4b2a6004/pruss@4b280000/mii-rt@4b2b2000        I  $/ocp/pruss-soc-bus@4b2a6004/pruss@4b280000/interrupt-controller@4b2a0000          8  $/ocp/pruss-soc-bus@4b2a6004/pruss@4b280000/pru@4b2b4000       8  $/ocp/pruss-soc-bus@4b2a6004/pruss@4b280000/pru@4b2b8000       9  $/ocp/pruss-soc-bus@4b2a6004/pruss@4b280000/mdio@4b2b2400            $/ocp/regulator-abb-mpu          %/ocp/regulator-abb-ivahd            %/ocp/regulator-abb-dspeve           %/ocp/regulator-abb-gpu          %/ocp/spi@48098000           %%/ocp/spi@4809a000           %,/ocp/spi@480b8000           %3/ocp/spi@480ba000           %:/ocp/qspi@4b300000        #  %?/ocp/ocp2scp@4a090000/phy@4a096000        '  %H/ocp/ocp2scp@4a090000/pciephy@4a094000        '  %R/ocp/ocp2scp@4a090000/pciephy@4a095000          %\/ocp/sata@4a141100          %a/ocp/rtc@48838000         #  %e/ocp/ocp2scp@4a080000/phy@4a084000        #  %o/ocp/ocp2scp@4a080000/phy@4a085000        #  %y/ocp/ocp2scp@4a080000/phy@4a084400          %/ocp/omap_dwc3_1@48880000         '  %/ocp/omap_dwc3_1@48880000/usb@48890000          %/ocp/omap_dwc3_2@488c0000         '  %/ocp/omap_dwc3_2@488c0000/usb@488d0000          %/ocp/omap_dwc3_3@48900000         '  %/ocp/omap_dwc3_3@48900000/usb@48910000          %/ocp/elm@48078000           %/ocp/gpmc@50000000          %/ocp/atl@4843c000           %/ocp/mcasp@48460000         %/ocp/mcasp@48464000         %/ocp/mcasp@48468000         %/ocp/mcasp@4846c000         %/ocp/mcasp@48470000         %/ocp/mcasp@48474000         %/ocp/mcasp@48478000         %/ocp/mcasp@4847c000         %/ocp/crossbar@4a002a48          /ocp/ethernet@48484000        %  &/ocp/ethernet@48484000/mdio@48485000          4  &/ocp/ethernet@48484000/mdio@48485000/ethernet-phy@2       4  &/ocp/ethernet@48484000/mdio@48485000/ethernet-phy@3       &  &)/ocp/ethernet@48484000/slave@48480200         &  &4/ocp/ethernet@48484000/slave@48480300         -  &?/ocp/ethernet@48484000/cpsw-phy-sel@4a002554            &G/ocp/can@4ae3c000           &M/ocp/can@48480000           %/ocp/gpu@56000000           &S/ocp/bb2d@59000000          &X/ocp/dss@58000000         #  #/ocp/dss@58000000/encoder@58060000        1  &\/ocp/dss@58000000/encoder@58060000/port/endpoint            &e/ocp/epwmss@4843e000          "  &m/ocp/epwmss@4843e000/pwm@4843e200         #  &u/ocp/epwmss@4843e000/ecap@4843e100          &{/ocp/epwmss@48440000          "  &/ocp/epwmss@48440000/pwm@48440200         #  &/ocp/epwmss@48440000/ecap@48440100          &/ocp/epwmss@48442000          "  &/ocp/epwmss@48442000/pwm@48442200         #  &/ocp/epwmss@48442000/ecap@48442100          &/ocp/aes@4b500000           &/ocp/aes@4b700000           &/ocp/des@480a5000           &/ocp/sham@53100000          &/ocp/rng@48090000           &/ocp/opp-supply@4a003b20            &/ocp/vip@0x48970000       !  &/ocp/vip@0x48970000/ports/port@0          !  &/ocp/vip@0x48970000/ports/port@1          ,  &/ocp/vip@0x48970000/ports/port@1/endpoint@0       !  &/ocp/vip@0x48970000/ports/port@2          !  &/ocp/vip@0x48970000/ports/port@3            &/ocp/cal@4845b000           &/ocp/cal@4845b000/ports/port@0        *  &/ocp/cal@4845b000/ports/port@0/endpoint@0           '/ocp/cal@4845b000/ports/port@1          '/thermal-zones          '/thermal-zones/cpu_thermal        !  ')/thermal-zones/cpu_thermal/trips          +  '3/thermal-zones/cpu_thermal/trips/cpu_alert        *  '>/thermal-zones/cpu_thermal/trips/cpu_crit         (  'G/thermal-zones/cpu_thermal/cooling-maps         'X/thermal-zones/gpu_thermal        *  'd/thermal-zones/gpu_thermal/trips/gpu_crit           'm/thermal-zones/core_thermal       ,  'z/thermal-zones/core_thermal/trips/core_crit         '/thermal-zones/dspeve_thermal         0  '/thermal-zones/dspeve_thermal/trips/dspeve_crit         '/thermal-zones/iva_thermal        *  '/thermal-zones/iva_thermal/trips/iva_crit           '/fixedregulator-evm12v0         '/fixedregulator-evm5v0          '/fixedregulator-evm_3v6         '/fixedregulator-vsys3v3         '/fixedregulator-evm_3v3         '/fixedregulator-aic_dvdd            '/fixedregulator-sd          '/extcon_usb1            (/extcon_usb2            (/connector          (/connector/port/endpoint          	  (%/encoder            (//encoder/ports/port@0/endpoint          (</encoder/ports/port@1/endpoint           /sound0         (J/sound0/simple-audio-card,cpu           (X/clk_ov10633_fixed          (j/fixedregulator-mmcwl         #  (w/reserved-memory/ipu2_cma@95800000        #  (/reserved-memory/dsp1_cma@99000000        #  (/reserved-memory/ipu1_cma@9d000000          (/fixedregulator-evm_1v8          	#address-cells #size-cells compatible interrupt-parent model stdout-path i2c0 i2c1 i2c2 i2c3 i2c4 serial0 serial1 serial2 serial3 serial4 serial5 serial6 serial7 serial8 serial9 ethernet0 ethernet1 d_can0 d_can1 spi0 rproc0 rproc1 rproc2 display0 sound0 sound1 interrupts interrupt-controller #interrupt-cells reg phandle device_type operating-points-v2 clocks clock-names clock-latency #cooling-cells vbb-supply vdd-supply syscon opp-hz opp-microvolt opp-supported-hw opp-suspend ti,hwmods ranges interrupts-extended regulator-name regulator-min-microvolt regulator-max-microvolt #clock-cells ti,bit-shift #pinctrl-cells pinctrl-single,register-width pinctrl-single,function-mask pinctrl-single,pins #syscon-cells #dma-cells dma-requests ti,dma-safe-map dma-masters clock-frequency clock-mult clock-div ti,max-div ti,autoidle-shift ti,index-starts-at-one ti,invert-autoidle-bit ti,index-power-of-two assigned-clocks assigned-clock-rates assigned-clock-parents ti,dividers reg-names bus-range num-lanes linux,pci-domain phys phy-names ti,syscon-lane-sel interrupt-map-mask interrupt-map status num-ib-windows num-ob-windows ti,syscon-unaligned-access #thermal-sensor-cells pinctrl-pin-array dma-channels interrupt-names ti,tptcs gpio-controller #gpio-cells dmas dma-names #mbox-cells ti,mbox-num-users ti,mbox-num-fifos ti,mbox-tx ti,mbox-rx ti,timer-alwon ti,timer-secure #hwlock-cells iommus ti,rproc-standby-info mboxes timers watchdog-timers memory-region syscon-bootreg lines-initial-states #sound-dai-cells adc-settle-ms ai3x-micbias-vg AVDD-supply IOVDD-supply DRVDD-supply DVDD-supply ti,system-power-controller smps1-in-supply smps2-in-supply smps3-in-supply smps4-in-supply smps5-in-supply ldo1-in-supply ldo2-in-supply ldo3-in-supply ldo4-in-supply ldo5-in-supply regulator-always-on regulator-boot-on regulator-allow-bypass wakeup-source ti,palmas-long-press-seconds gpio-hog gpios output-low line-name mux-gpios remote-endpoint hsync-active vsync-active pclk-sample clock-lanes data-lanes pbias-supply max-frequency mmc-ddr-1_8v mmc-ddr-3_3v pinctrl-names pinctrl-0 vmmc-supply bus-width cd-gpios vqmmc-supply pinctrl-1 pinctrl-2 pinctrl-3 pinctrl-4 pinctrl-5 pinctrl-6 sdhci-caps-mask mmc-hs200-1_8v non-removable cap-power-off-card keep-power-in-suspend #iommu-cells ti,syscon-mmuconfig ti,iommu-bus-err-back firmware-name bus_freq ti,settling-time ti,clock-cycles ti,tranxdone-status-mask ti,ldovbb-override-mask ti,ldovbb-vset-mask ti,abb_info ti,spi-num-cs syscon-chipselects spi-max-frequency spi-tx-bus-width spi-rx-bus-width label syscon-phy-power syscon-pllreset #phy-cells syscon-pcs ports-implemented phy-supply ti,sysc-mask ti,sysc-sidle utmi-mode extcon maximum-speed dr_mode snps,dis_u3_susphy_quirk snps,dis_u2_susphy_quirk snps,dis_metastability_quirk gpmc,num-cs gpmc,num-waitpins rb-gpios ti,nand-xfer-type ti,nand-ecc-opt ti,elm-id nand-bus-width gpmc,device-width gpmc,sync-clk-ps gpmc,cs-on-ns gpmc,cs-rd-off-ns gpmc,cs-wr-off-ns gpmc,adv-on-ns gpmc,adv-rd-off-ns gpmc,adv-wr-off-ns gpmc,we-on-ns gpmc,we-off-ns gpmc,oe-on-ns gpmc,oe-off-ns gpmc,access-ns gpmc,wr-access-ns gpmc,rd-cycle-ns gpmc,wr-cycle-ns gpmc,bus-turnaround-ns gpmc,cycle2cycle-delay-ns gpmc,clk-activation-ns gpmc,wr-data-mux-bus-ns ti,provided-clocks bws aws op-mode tdm-slots serial-dir tx-num-evt rx-num-evt ti,max-irqs ti,max-crossbar-sources ti,reg-size ti,irqs-reserved ti,irqs-skip ti,irqs-safe-map cpdma_channels ale_entries bd_ram_size mac_control slaves active_slave cpts_clock_mult cpts_clock_shift ti,no-idle mode-gpios dual_emac ti,rx-internal-delay ti,tx-internal-delay ti,fifo-depth ti,min-output-impedance ti,dp83867-rxctrl-strap-quirk mac-address phy_id phy-mode dual_emac_res_vlan syscon-raminit syscon-pll-ctrl vdda_video-supply syscon-pol vdda-supply #pwm-cells ti,efuse-settings ti,absolute-max-voltage-uv slave-mode syscon-camerrx polling-delay-passive polling-delay thermal-sensors coefficients temperature hysteresis trip cooling-device vin-supply enable-active-high gpio id-gpio simple-audio-card,name simple-audio-card,widgets simple-audio-card,routing simple-audio-card,format simple-audio-card,bitclock-master simple-audio-card,frame-master simple-audio-card,bitclock-inversion sound-dai system-clock-frequency reusable gic wakeupgen cpu0 cpu0_opp_table l4_cfg scm scm_conf pbias_regulator pbias_mmc_reg scm_conf_clocks dss_deshdcp_clk ehrpwm0_tbclk ehrpwm1_tbclk ehrpwm2_tbclk sys_32k_ck dra7_pmx_core dcan1_pins_default dcan1_pins_sleep mmc1_pins_default mmc1_pins_sdr12 mmc1_pins_hs mmc1_pins_sdr25 mmc1_pins_sdr50 mmc1_pins_ddr50_rev10 mmc1_pins_ddr50_rev20 mmc1_pins_sdr104 mmc2_pins_default mmc2_pins_hs mmc2_pins_ddr_rev10 mmc2_pins_ddr_rev20 mmc2_pins_hs200 mmc4_pins_default scm_conf1 scm_conf_pcie sdma_xbar edma_xbar dra72_vip_mux cm_core_aon cm_core_aon_clocks atl_clkin0_ck atl_clkin1_ck atl_clkin2_ck atl_clkin3_ck hdmi_clkin_ck mlb_clkin_ck mlbp_clkin_ck pciesref_acs_clk_ck ref_clkin0_ck ref_clkin1_ck ref_clkin2_ck ref_clkin3_ck rmii_clk_ck sdvenc_clkin_ck secure_32k_clk_src_ck sys_clk32_crystal_ck sys_clk32_pseudo_ck virt_12000000_ck virt_13000000_ck virt_16800000_ck virt_19200000_ck virt_20000000_ck virt_26000000_ck virt_27000000_ck virt_38400000_ck sys_clkin2 usb_otg_clkin_ck video1_clkin_ck video1_m2_clkin_ck video2_clkin_ck video2_m2_clkin_ck dpll_abe_ck dpll_abe_x2_ck dpll_abe_m2x2_ck abe_clk dpll_abe_m2_ck dpll_abe_m3x2_ck dpll_core_byp_mux dpll_core_ck dpll_core_x2_ck dpll_core_h12x2_ck mpu_dpll_hs_clk_div dpll_mpu_ck dpll_mpu_m2_ck mpu_dclk_div dsp_dpll_hs_clk_div dpll_dsp_byp_mux dpll_dsp_ck dpll_dsp_m2_ck iva_dpll_hs_clk_div dpll_iva_byp_mux dpll_iva_ck dpll_iva_m2_ck iva_dclk dpll_gpu_byp_mux dpll_gpu_ck dpll_gpu_m2_ck dpll_core_m2_ck core_dpll_out_dclk_div dpll_ddr_byp_mux dpll_ddr_ck dpll_ddr_m2_ck dpll_gmac_byp_mux dpll_gmac_ck dpll_gmac_m2_ck video2_dclk_div video1_dclk_div hdmi_dclk_div per_dpll_hs_clk_div usb_dpll_hs_clk_div eve_dpll_hs_clk_div dpll_eve_byp_mux dpll_eve_ck dpll_eve_m2_ck eve_dclk_div dpll_core_h13x2_ck dpll_core_h14x2_ck dpll_core_h22x2_ck dpll_core_h23x2_ck dpll_core_h24x2_ck dpll_ddr_x2_ck dpll_ddr_h11x2_ck dpll_dsp_x2_ck dpll_dsp_m3x2_ck dpll_gmac_x2_ck dpll_gmac_h11x2_ck dpll_gmac_h12x2_ck dpll_gmac_h13x2_ck dpll_gmac_m3x2_ck gmii_m_clk_div hdmi_clk2_div hdmi_div_clk l3_iclk_div l4_root_clk_div video1_clk2_div video1_div_clk video2_clk2_div video2_div_clk dummy_ck cm_core_aon_clockdomains mpu_cm mpu_clkctrl dsp1_cm dsp1_clkctrl ipu1_cm ipu1_clkctrl ipu_cm ipu_clkctrl dsp2_cm dsp2_clkctrl rtc_cm rtc_clkctrl cm_core cm_core_clocks dpll_pcie_ref_ck dpll_pcie_ref_m2ldo_ck apll_pcie_in_clk_mux apll_pcie_ck optfclk_pciephy_div apll_pcie_clkvcoldo apll_pcie_clkvcoldo_div apll_pcie_m2_ck dpll_per_byp_mux dpll_per_ck dpll_per_m2_ck func_96m_aon_dclk_div dpll_usb_byp_mux dpll_usb_ck dpll_usb_m2_ck dpll_pcie_ref_m2_ck dpll_per_x2_ck dpll_per_h11x2_ck dpll_per_h12x2_ck dpll_per_h13x2_ck dpll_per_h14x2_ck dpll_per_m2x2_ck dpll_usb_clkdcoldo func_128m_clk func_12m_fclk func_24m_clk func_48m_fclk func_96m_fclk l3init_60m_fclk clkout2_clk l3init_960m_gfclk usb_phy1_always_on_clk32k usb_phy2_always_on_clk32k usb_phy3_always_on_clk32k gpu_core_gclk_mux gpu_hyd_gclk_mux l3instr_ts_gclk_div vip1_gclk_mux vip2_gclk_mux vip3_gclk_mux cm_core_clockdomains coreaon_clkdm coreaon_cm coreaon_clkctrl l3main1_cm l3main1_clkctrl ipu2_cm ipu2_clkctrl dma_cm dma_clkctrl emif_cm emif_clkctrl atl_cm atl_clkctrl l4cfg_cm l4cfg_clkctrl l3instr_cm l3instr_clkctrl dss_cm dss_clkctrl l3init_cm l3init_clkctrl l4per_cm l4per_clkctrl l4_wkup counter32k prm prm_clocks sys_clkin1 abe_dpll_sys_clk_mux abe_dpll_bypass_clk_mux abe_dpll_clk_mux abe_24m_fclk aess_fclk abe_giclk_div abe_lp_clk_div abe_sys_clk_div adc_gfclk_mux sys_clk1_dclk_div sys_clk2_dclk_div per_abe_x1_dclk_div dsp_gclk_div gpu_dclk emif_phy_dclk_div gmac_250m_dclk_div gmac_main_clk l3init_480m_dclk_div usb_otg_dclk_div sata_dclk_div pcie2_dclk_div pcie_dclk_div emu_dclk_div secure_32k_dclk_div clkoutmux0_clk_mux clkoutmux1_clk_mux clkoutmux2_clk_mux custefuse_sys_gfclk_div eve_clk hdmi_dpll_clk_mux mlb_clk mlbp_clk per_abe_x1_gfclk2_div timer_sys_clk_div video1_dpll_clk_mux video2_dpll_clk_mux wkupaon_iclk_mux prm_clockdomains wkupaon_cm wkupaon_clkctrl scm_wkup pcie1_rc pcie1_intc pcie1_ep pcie2_rc pcie2_intc ocmcram1 ocmcram2 ocmcram3 bandgap dsp1_system dra7_iodelay_core mmc1_iodelay_ddr50_conf mmc1_iodelay_sdr104_rev10_conf mmc1_iodelay_sdr104_rev20_conf mmc2_iodelay_ddr_conf mmc2_iodelay_hs200_rev10_conf mmc2_iodelay_hs200_rev20_conf sdma edma edma_tptc0 edma_tptc1 gpio1 gpio2 gpio3 gpio4 gpio5 gpio6 gpio7 gpio8 uart1 uart2 uart3 uart4 uart5 uart6 uart7 uart8 uart9 uart10 mailbox1 mailbox2 mailbox3 mailbox4 mailbox5 mbox_ipu1_ipc3x mbox_dsp1_ipc3x mailbox6 mbox_ipu2_ipc3x mailbox7 mailbox8 mailbox9 mailbox10 mailbox11 mailbox12 mailbox13 timer1 timer2 timer3 timer4 timer5 timer6 timer7 timer8 timer9 timer10 timer11 timer12 timer13 timer14 timer15 timer16 wdt2 hwspinlock ipu1 ipu2 dsp1 pcf_lcd pcf_gpio_21 tlv320aic3106 tps65917 tps65917_regulators smps1_reg smps2_reg smps3_reg smps4_reg smps5_reg ldo1_reg ldo2_reg ldo3_reg ldo5_reg ldo4_reg i2c5 pcf_hdmi onboardLI gpio_csi2_adap csi2_cam0 mmc1 hdqw1w mmc2 mmc3 mmc4 mmu0_dsp1 mmu1_dsp1 mmu_ipu1 mmu_ipu2 pruss_soc_bus1 pruss1 pruss1_mem pruss1_cfg pruss1_iep pruss1_mii_rt pruss1_intc pru1_0 pru1_1 pruss1_mdio pruss_soc_bus2 pruss2 pruss2_mem pruss2_cfg pruss2_iep pruss2_mii_rt pruss2_intc pru2_0 pru2_1 pruss2_mdio abb_mpu abb_ivahd abb_dspeve abb_gpu mcspi1 mcspi2 mcspi3 mcspi4 qspi sata_phy pcie1_phy pcie2_phy sata rtc usb2_phy1 usb2_phy2 usb3_phy1 omap_dwc3_1 usb1 omap_dwc3_2 usb2 omap_dwc3_3 usb3 elm gpmc atl mcasp1 mcasp2 mcasp3 mcasp4 mcasp5 mcasp6 mcasp7 mcasp8 crossbar_mpu davinci_mdio dp83867_0 dp83867_1 cpsw_emac0 cpsw_emac1 phy_sel dcan1 dcan2 bb2d dss hdmi_out epwmss0 ehrpwm0 ecap0 epwmss1 ehrpwm1 ecap1 epwmss2 ehrpwm2 ecap2 aes1 aes2 des sham rng opp_supply_mpu vip1 vin1a vin2a vin2a_ep vin1b vin2b cal csi2_0 csi2_phy0 csi2_1 thermal_zones cpu_thermal cpu_trips cpu_alert0 cpu_crit cpu_cooling_maps gpu_thermal gpu_crit core_thermal core_crit dspeve_thermal dspeve_crit iva_thermal iva_crit evm_12v0 evm_5v0 evm_3v6 vsys_3v3 evm_3v3_sw aic_dvdd evm_3v3_sd extcon_usb1 extcon_usb2 hdmi0 hdmi_connector_in tpd12s015 tpd12s015_in tpd12s015_out sound0_master clk_ov10633_fixed vmmcwl_fixed ipu2_cma_pool dsp1_cma_pool ipu1_cma_pool evm_1v8_sw display1 leds brightness-levels default-brightness-level enable-gpios reset-gpios data-lines touchscreen-size-x touchscreen-size-y lcd_bl tc358768_refclk dsi_bridge dsi_bridge_ports rgb_in tlc59108 backlight_led pcf_display_board touchscreen dpi_out backlight lcd_in dsi_out 