 f   8 l   (            ' 4                                                         ti,dra76-evm ti,dra762 ti,dra7           &            7TI DRA762 EVM      connector@0         A  
        '                  '           '        	dvi          dvi-connector     port       endpoint            A                        encoder@0           A  	      
   ti,tfp410     ports                                port@1          =      endpoint@0          A                     port@0          =       endpoint@0          A                           chosen           =/ocp/serial@4806a000          aliases         'z/connector 0         I/ocp/i2c@48070000            N/ocp/i2c@48072000            S/ocp/i2c@48060000            X/ocp/i2c@4807a000            ]/ocp/i2c@4807c000            b/ocp/serial@4806a000             j/ocp/serial@4806c000             r/ocp/serial@48020000             z/ocp/serial@4806e000             /ocp/serial@48066000             /ocp/serial@48068000             /ocp/serial@48420000             /ocp/serial@48422000             /ocp/serial@48424000             /ocp/serial@4ae2b000          &   /ocp/ethernet@48484000/slave@48480200         &   /ocp/ethernet@48484000/slave@48480300            /ocp/can@4ae3c000            /ocp/can@48480000            /ocp/qspi@4b300000           /ocp/ipu@58820000            /ocp/ipu@55020000            /ocp/dsp@40800000            /ocp/dsp@41000000         	   /display r           /sound0       #  /ocp/dss@58000000/encoder@58060000        timer            arm,armv7-timer       0                                
           &         interrupt-controller@48211000            arm,cortex-a15-gic                   ,         @  =    H!            H!              H!@             H!`                       	           &           A         interrupt-controller@48281000         &   ti,omap5-wugen-mpu ti,omap4-wugen-mpu                    ,           =    H(                 &           A         cpus                                 cpu@0           Icpu          arm,cortex-a15          =            U           i           pcpu         |                                          A         cpu@1           Icpu          arm,cortex-a15          =           U           i           pcpu         |                                opp-table            operating-points-v2-ti-cpu                              A      opp_nom-1000000000              ;          , P 0 , P 0                             opp_od-1176000000               FV          @  @ @  @                    opp_high@1500000000             Yh/          v ~  v ~                     opp_plus@1800000000             kI           ~   ~                        soc          ti,omap-infra      mpu          ti,omap5-mpu            mpu          ocp          ti,dra7-l3-noc simple-bus                                                           l3_main_1 l3_main_2          =    D              E                                          
      l4@4a000000          ti,dra7-l4-cfg simple-bus                                        J    "         A      scm@2000             ti,dra7-scm-core simple-bus         =                                                             A      scm_conf@0           syscon simple-bus           =                                                           A   	   pbias_regulator@e00          ti,pbias-dra7 ti,pbias-omap         =                 	        A      pbias_mmc_omap5         pbias_mmc_omap5         ' w@        ? 2Z        A            clocks                                    A      dss_deshdcp_clk@558         W             ti,gate-clock           i   
        d            =  X        A         ehrpwm0_tbclk@558           W             ti,gate-clock           i           d           =  X        A         ehrpwm1_tbclk@558           W             ti,gate-clock           i           d           =  X        A         ehrpwm2_tbclk@558           W             ti,gate-clock           i           d           =  X        A         sys_32k_ck          W             ti,mux-clock            i                    d           =          A   R      dpll_gmac_h14x2_ctrl_ck@3fc         W             ti,divider-clock            i           q   ?        =          d           |                      Ĵ         A         dpll_gmac_h14x2_ctrl_mux_ck@3fc         W             ti,mux-clock            i              =          d           |                                 A         mcan_clk@3fc            W             ti,gate-clock           i           d           =          A               pinmux@1400          ti,dra7-padconf pinctrl-single          =     h                                             ,                                ?        A      mmc1_pins_default         0    T     X     \     `     d     h           A         mmc1_pins_hs          0    T   X   \   `   d   h         A         mmc1_pins_sdr50       0    T   X   \   `   d   h         A         mmc1_pins_ddr50       0    T    X    \    `    d    h          A         mmc2_pins_default         P                                                            A         mmc2_pins_hs200       P                                                  A         mmc3_pins_default         0    |                              A         mmc4_pins_hs          0                            A            scm_conf@1c04            syscon          =              #           A         scm_conf@1c24            syscon          =  $   $        A         dma-router@b78           ti,dra7-dma-crossbar            =  x           1           <           I            Y           A         dma-router@c78           ti,dra7-dma-crossbar            =  x   |        1           <           I            Y           A            cm_core_aon@5000             ti,dra7-cm-core-aon simple-bus                                   =  P                   P             A      clocks                                    A      atl_clkin0_ck           W             ti,dra7-atl-clock           i                  A         atl_clkin1_ck           W             ti,dra7-atl-clock           i                  A         atl_clkin2_ck           W             ti,dra7-atl-clock           i                  A         atl_clkin3_ck           W             ti,dra7-atl-clock           i                  A         hdmi_clkin_ck           W             fixed-clock         e            A   3      mlb_clkin_ck            W             fixed-clock         e            A         mlbp_clkin_ck           W             fixed-clock         e            A         pciesref_acs_clk_ck         W             fixed-clock         e         A   B      ref_clkin0_ck           W             fixed-clock         e            A         ref_clkin1_ck           W             fixed-clock         e            A        ref_clkin2_ck           W             fixed-clock         e            A        ref_clkin3_ck           W             fixed-clock         e            A        rmii_clk_ck         W             fixed-clock         e            A        sdvenc_clkin_ck         W             fixed-clock         e            A        secure_32k_clk_src_ck           W             fixed-clock         e           A   m      sys_clk32_crystal_ck            W             fixed-clock         e           A         sys_clk32_pseudo_ck         W             fixed-factor-clock          i           u             b        A         virt_12000000_ck            W             fixed-clock         e          A   [      virt_13000000_ck            W             fixed-clock         e ]@        A        virt_16800000_ck            W             fixed-clock         e Y         A   ]      virt_19200000_ck            W             fixed-clock         e$         A   ^      virt_20000000_ck            W             fixed-clock         e1-         A   \      virt_26000000_ck            W             fixed-clock         e        A   _      virt_27000000_ck            W             fixed-clock         e        A   `      virt_38400000_ck            W             fixed-clock         eI         A   a      sys_clkin2          W             fixed-clock         eX         A   b      usb_otg_clkin_ck            W             fixed-clock         e            A   j      video1_clkin_ck         W             fixed-clock         e            A   <      video1_m2_clkin_ck          W             fixed-clock         e            A   2      video2_clkin_ck         W             fixed-clock         e            A   =      video2_m2_clkin_ck          W             fixed-clock         e            A   1      dpll_abe_ck@1e0         W             ti,omap4-dpll-m4xen-clock           i              =                A         dpll_abe_x2_ck          W             ti,omap4-dpll-x2-clock          i           A         dpll_abe_m2x2_ck@1f0            W             ti,divider-clock            i           q                      =                            A         abe_clk@108         W             ti,divider-clock            i           q           =                   A   d      dpll_abe_m2_ck@1f0          W             ti,divider-clock            i           q                      =                            A   f      dpll_abe_m3x2_ck@1f4            W             ti,divider-clock            i           q                      =                            A         dpll_core_byp_mux@12c           W             ti,mux-clock            i              d           =  ,        A         dpll_core_ck@120            W             ti,omap4-dpll-core-clock            i              =     $  ,  (        A         dpll_core_x2_ck         W             ti,omap4-dpll-x2-clock          i           A         dpll_core_h12x2_ck@13c          W             ti,divider-clock            i           q   ?                   =  <                          A         mpu_dpll_hs_clk_div         W             fixed-factor-clock          i           u                      A          dpll_mpu_ck@160         W             ti,omap5-mpu-dpll-clock         i               =  `  d  l  h        A         dpll_mpu_m2_ck@170          W             ti,divider-clock            i           q                      =  p                          A   !      mpu_dclk_div            W             fixed-factor-clock          i   !        u                      A   q      dsp_dpll_hs_clk_div         W             fixed-factor-clock          i           u                      A   "      dpll_dsp_byp_mux@240            W             ti,mux-clock            i      "        d           =  @        A   #      dpll_dsp_ck@234         W             ti,omap4-dpll-clock         i      #        =  4  8  @  <           $        #F         A   $      dpll_dsp_m2_ck@244          W             ti,divider-clock            i   $        q                      =  D                             %        #F         A   %      iva_dpll_hs_clk_div         W             fixed-factor-clock          i           u                      A   &      dpll_iva_byp_mux@1ac            W             ti,mux-clock            i      &        d           =          A   '      dpll_iva_ck@1a0         W             ti,omap4-dpll-clock         i      '        =                   (        Ep}@        A   (      dpll_iva_m2_ck@1b0          W             ti,divider-clock            i   (        q                      =                               )        %        A   )      iva_dclk            W             fixed-factor-clock          i   )        u                      A   s      dpll_gpu_byp_mux@2e4            W             ti,mux-clock            i              d           =          A   *      dpll_gpu_ck@2d8         W             ti,omap4-dpll-clock         i      *        =                   +        Ly@        A   +      dpll_gpu_m2_ck@2e8          W             ti,divider-clock            i   +        q                      =                               ,        _(k        A   ,      dpll_core_m2_ck@130         W             ti,divider-clock            i           q                      =  0                          A   -      core_dpll_out_dclk_div          W             fixed-factor-clock          i   -        u                      A   u      dpll_ddr_byp_mux@21c            W             ti,mux-clock            i              d           =          A   .      dpll_ddr_ck@210         W             ti,omap4-dpll-clock         i      .        =                A   /      dpll_ddr_m2_ck@220          W             ti,divider-clock            i   /        q                      =                             A   g      dpll_gmac_byp_mux@2b4           W             ti,mux-clock            i              d           =          A   0      dpll_gmac_ck@2a8            W             ti,omap4-dpll-clock         i      0        =                A         dpll_gmac_m2_ck@2b8         W             ti,divider-clock            i           q                      =                            A   h      video2_dclk_div         W             fixed-factor-clock          i   1        u                      A   w      video1_dclk_div         W             fixed-factor-clock          i   2        u                      A   x      hdmi_dclk_div           W             fixed-factor-clock          i   3        u                      A   y      per_dpll_hs_clk_div         W             fixed-factor-clock          i           u                      A   E      usb_dpll_hs_clk_div         W             fixed-factor-clock          i           u                      A   I      eve_dpll_hs_clk_div         W             fixed-factor-clock          i           u                      A   4      dpll_eve_byp_mux@290            W             ti,mux-clock            i      4        d           =          A   5      dpll_eve_ck@284         W             ti,omap4-dpll-clock         i      5        =                A   6      dpll_eve_m2_ck@294          W             ti,divider-clock            i   6        q                      =                            A   7      eve_dclk_div            W             fixed-factor-clock          i   7        u                      A         dpll_core_h13x2_ck@140          W             ti,divider-clock            i           q   ?                   =  @                          A        dpll_core_h14x2_ck@144          W             ti,divider-clock            i           q   ?                   =  D                          A   S      dpll_core_h22x2_ck@154          W             ti,divider-clock            i           q   ?                   =  T                          A   ?      dpll_core_h23x2_ck@158          W             ti,divider-clock            i           q   ?                   =  X                          A   X      dpll_core_h24x2_ck@15c          W             ti,divider-clock            i           q   ?                   =  \                          A        dpll_ddr_x2_ck          W             ti,omap4-dpll-x2-clock          i   /        A   8      dpll_ddr_h11x2_ck@228           W             ti,divider-clock            i   8        q   ?                   =  (                          A  	      dpll_dsp_x2_ck          W             ti,omap4-dpll-x2-clock          i   $        A   9      dpll_dsp_m3x2_ck@248            W             ti,divider-clock            i   9        q                      =  H                             :        ׄ         A   :      dpll_gmac_x2_ck         W             ti,omap4-dpll-x2-clock          i           A         dpll_gmac_h11x2_ck@2c0          W             ti,divider-clock            i           q   ?                   =                            A   ;      dpll_gmac_h12x2_ck@2c4          W             ti,divider-clock            i           q   ?                   =                            A  
      dpll_gmac_h13x2_ck@2c8          W             ti,divider-clock            i           q   ?                   =                            A         dpll_gmac_m3x2_ck@2bc           W             ti,divider-clock            i           q                      =                            A        gmii_m_clk_div          W             fixed-factor-clock          i   ;        u                      A        hdmi_clk2_div           W             fixed-factor-clock          i   3        u                      A        hdmi_div_clk            W             fixed-factor-clock          i   3        u                      A        l3_iclk_div@100         W             ti,divider-clock            q           d           =           i                    A   
      l4_root_clk_div         W             fixed-factor-clock          i   
        u                      A         video1_clk2_div         W             fixed-factor-clock          i   <        u                      A        video1_div_clk          W             fixed-factor-clock          i   <        u                      A        video2_clk2_div         W             fixed-factor-clock          i   =        u                      A        video2_div_clk          W             fixed-factor-clock          i   =        u                      A        dummy_ck            W             fixed-clock         e            A           clockdomains            A        mpu_cm@300           ti,omap4-cm         =                                                         A     clk@20           ti,clkctrl          =               W           A           dsp1_cm@400          ti,omap4-cm         =                                                         A     clk@20           ti,clkctrl          =               W           A           ipu1_cm@500          ti,omap4-cm         =      @                                                   A     clk@20           ti,clkctrl          =                W              >                  ?        A   >         ipu_cm@540           ti,omap4-cm         =  @                                          @           A     clk@0            ti,clkctrl          =       D        W           A            dsp2_cm@600          ti,omap4-cm         =                                                         A     clk@20           ti,clkctrl          =               W           A           rtc_cm@700           ti,omap4-cm         =                                                         A     clk@40           ti,clkctrl          =   @           W           A              cm_core@8000             ti,dra7-cm-core simple-bus                                   =     0                  0         A     clocks                                    A      dpll_pcie_ref_ck@200            W             ti,omap4-dpll-clock         i              =                 A   @      dpll_pcie_ref_m2ldo_ck@210          W             ti,divider-clock            i   @        q                      =                            A   A      apll_pcie_in_clk_mux@4ae06118            ti,mux-clock            i   A   B        W            =             d           A   C      apll_pcie_ck@21c            W             ti,dra7-apll-clock          i   C   @        =             A   D      optfclk_pciephy_div@4a00821c             ti,divider-clock            i   D        W            =                        d           q           A         apll_pcie_clkvcoldo         W             fixed-factor-clock          i   D        u                      A  !      apll_pcie_clkvcoldo_div         W             fixed-factor-clock          i   D        u                      A  "      apll_pcie_m2_ck         W             fixed-factor-clock          i   D        u                      A   l      dpll_per_byp_mux@14c            W             ti,mux-clock            i      E        d           =  L        A   F      dpll_per_ck@140         W             ti,omap4-dpll-clock         i      F        =  @  D  L  H        A   G      dpll_per_m2_ck@150          W             ti,divider-clock            i   G        q                      =  P                          A   H      func_96m_aon_dclk_div           W             fixed-factor-clock          i   H        u                      A   z      dpll_usb_byp_mux@18c            W             ti,mux-clock            i      I        d           =          A   J      dpll_usb_ck@180         W             ti,omap4-dpll-j-type-clock          i      J        =                A   K      dpll_usb_m2_ck@190          W             ti,divider-clock            i   K        q                      =                            A   O      dpll_pcie_ref_m2_ck@210         W             ti,divider-clock            i   @        q                      =                            A   k      dpll_per_x2_ck          W             ti,omap4-dpll-x2-clock          i   G        A   L      dpll_per_h11x2_ck@158           W             ti,divider-clock            i   L        q   ?                   =  X                          A   M      dpll_per_h12x2_ck@15c           W             ti,divider-clock            i   L        q   ?                   =  \                          A  #      dpll_per_h13x2_ck@160           W             ti,divider-clock            i   L        q   ?                   =  `                          A  $      dpll_per_h14x2_ck@164           W             ti,divider-clock            i   L        q   ?                   =  d                          A   T      dpll_per_m2x2_ck@150            W             ti,divider-clock            i   L        q                      =  P                          A   N      dpll_usb_clkdcoldo          W             fixed-factor-clock          i   K        u                      A   Q      func_128m_clk           W             fixed-factor-clock          i   M        u                      A  %      func_12m_fclk           W             fixed-factor-clock          i   N        u                      A  &      func_24m_clk            W             fixed-factor-clock          i   H        u                      A  '      func_48m_fclk           W             fixed-factor-clock          i   N        u                      A  (      func_96m_fclk           W             fixed-factor-clock          i   N        u                      A  )      l3init_60m_fclk@104         W             ti,divider-clock            i   O        =                        A  *      clkout2_clk@6b0         W             ti,gate-clock           i   P        d           =          A  +      l3init_960m_gfclk@6c0           W             ti,gate-clock           i   Q        d           =          A  ,      usb_phy1_always_on_clk32k@640           W             ti,gate-clock           i   R        d           =  @        A         usb_phy2_always_on_clk32k@688           W             ti,gate-clock           i   R        d           =          A         usb_phy3_always_on_clk32k@698           W             ti,gate-clock           i   R        d           =          A         gpu_core_gclk_mux@1220          W             ti,mux-clock            i   S   T   ,        d           =              U           ,        A   U      gpu_hyd_gclk_mux@1220           W             ti,mux-clock            i   S   T   ,        d           =              V           ,        A   V      l3instr_ts_gclk_div@e50         W             ti,divider-clock            i   W        d           =  P                          A  -      vip1_gclk_mux@1020          W             ti,mux-clock            i   
   X        d           =           A  .      vip2_gclk_mux@1028          W             ti,mux-clock            i   
   X        d           =  (        A  /      vip3_gclk_mux@1030          W             ti,mux-clock            i   
   X        d           =  0        A  0         clockdomains            A  1   coreaon_clkdm            ti,clockdomain          i   K        A  2         coreaon_cm@600           ti,omap4-cm         =                                                         A  3   clk@20           ti,clkctrl          =               W           A            l3main1_cm@700           ti,omap4-cm         =                                                         A  4   clk@20           ti,clkctrl          =       t        W           A  5         ipu2_cm@900          ti,omap4-cm         =  	                                           	            A  6   clk@20           ti,clkctrl          =               W           A  7         dma_cm@a00           ti,omap4-cm         =  
                                           
            A  8   clk@20           ti,clkctrl          =               W           A  9         emif_cm@b00          ti,omap4-cm         =                                                         A  :   clk@20           ti,clkctrl          =               W           A  ;         atl_cm@c00           ti,omap4-cm         =                                                         A  <   clk@0            ti,clkctrl          =               W           A            l4cfg_cm@d00             ti,omap4-cm         =                                                         A  =   clk@20           ti,clkctrl          =               W           A  >         l3instr_cm@e00           ti,omap4-cm         =                                                         A  ?   clk@20           ti,clkctrl          =               W           A  @         dss_cm@1100          ti,omap4-cm         =                                                         A  A   clk@20           ti,clkctrl          =               W           A            l3init_cm@1300           ti,omap4-cm         =                                                         A  B   clk@20           ti,clkctrl          =               W           A            l4per_cm@1700            ti,omap4-cm         =                                                         A  C   clk@0            ti,clkctrl          =              W              Y  h              Z        A   Y               l4@4ae00000          ti,dra7-l4-wkup simple-bus                                       J            A  D   counter@4000             ti,omap-counter32k          =  @    @        counter_32k         A  E      prm@6000             ti,dra7-prm simple-bus          =  `   0                                                          `   0         A  F   clocks                                    A  G   sys_clkin1@110          W             ti,mux-clock            i   [   \   ]   ^   _   `   a        =                   A         abe_dpll_sys_clk_mux@118            W             ti,mux-clock            i      b        =          A   c      abe_dpll_bypass_clk_mux@114         W             ti,mux-clock            i   c   R        =          A         abe_dpll_clk_mux@10c            W             ti,mux-clock            i   c   R        =          A         abe_24m_fclk@11c            W             ti,divider-clock            i           =                        A   Z      aess_fclk@178           W             ti,divider-clock            i   d        =  x        q           A   e      abe_giclk_div@174           W             ti,divider-clock            i   e        =  t        q           A  H      abe_lp_clk_div@1d8          W             ti,divider-clock            i           =                         A         abe_sys_clk_div@120         W             ti,divider-clock            i           =           q           A  I      adc_gfclk_mux@1dc           W             ti,mux-clock            i      b   R        =          A  J      sys_clk1_dclk_div@1c8           W             ti,divider-clock            i           q   @        =                   A   n      sys_clk2_dclk_div@1cc           W             ti,divider-clock            i   b        q   @        =                   A   o      per_abe_x1_dclk_div@1bc         W             ti,divider-clock            i   f        q   @        =                   A   p      dsp_gclk_div@18c            W             ti,divider-clock            i   %        q   @        =                   A   r      gpu_dclk@1a0            W             ti,divider-clock            i   ,        q   @        =                   A   t      emif_phy_dclk_div@190           W             ti,divider-clock            i   g        q   @        =                   A   v      gmac_250m_dclk_div@19c          W             ti,divider-clock            i   h        q   @        =                   A   i      gmac_main_clk           W             fixed-factor-clock          i   i        u                      A         l3init_480m_dclk_div@1ac            W             ti,divider-clock            i   O        q   @        =                   A   {      usb_otg_dclk_div@184            W             ti,divider-clock            i   j        q   @        =                   A   |      sata_dclk_div@1c0           W             ti,divider-clock            i           q   @        =                   A   }      pcie2_dclk_div@1b8          W             ti,divider-clock            i   k        q   @        =                   A   ~      pcie_dclk_div@1b4           W             ti,divider-clock            i   l        q   @        =                   A         emu_dclk_div@194            W             ti,divider-clock            i           q   @        =                   A         secure_32k_dclk_div@1c4         W             ti,divider-clock            i   m        q   @        =                   A         clkoutmux0_clk_mux@158          W             ti,mux-clock          X  i   n   o   p   q   r   s   t   u   v   i   w   x   y   z   {   |   }   ~                    =  X        A  K      clkoutmux1_clk_mux@15c          W             ti,mux-clock          X  i   n   o   p   q   r   s   t   u   v   i   w   x   y   z   {   |   }   ~                    =  \        A  L      clkoutmux2_clk_mux@160          W             ti,mux-clock          X  i   n   o   p   q   r   s   t   u   v   i   w   x   y   z   {   |   }   ~                    =  `        A   P      custefuse_sys_gfclk_div         W             fixed-factor-clock          i           u                      A  M      eve_clk@180         W             ti,mux-clock            i   7   :        =          A  N      hdmi_dpll_clk_mux@164           W             ti,mux-clock            i      b        =  d        A  O      mlb_clk@134         W             ti,divider-clock            i           q   @        =  4                 A  P      mlbp_clk@130            W             ti,divider-clock            i           q   @        =  0                 A  Q      per_abe_x1_gfclk2_div@138           W             ti,divider-clock            i   f        q   @        =  8                 A  R      timer_sys_clk_div@144           W             ti,divider-clock            i           =  D        q           A  S      video1_dpll_clk_mux@168         W             ti,mux-clock            i      b        =  h        A  T      video2_dpll_clk_mux@16c         W             ti,mux-clock            i      b        =  l        A  U      wkupaon_iclk_mux@108            W             ti,mux-clock            i              =          A   W         clockdomains            A  V      wkupaon_cm@1800          ti,omap4-cm         =                                                         A  W   clk@20           ti,clkctrl          =       l        W           A               scm_conf@c000            syscon          =              A            axi@0            simple-bus                                   Q   Q     0               pcie@51000000           =Q       Q     L               rc_dbics ti_conf config                                                              Ipci       0               0                0  0                             ,                       
            pcie1                          pcie-phy0 pcie-phy1         *              =                     `  P                                                                                            ^okay             ti,dra746-pcie-rc ti,dra7-pcie          A  X   interrupt-controller                                   ,           A            pcie_ep@51000000             =Q      (Q     LQ     (            &  ep_dbics ti_conf ep_dbics2 addr_space                                         e           t           pcie1                          pcie-phy0 pcie-phy1                          *            	  ^disabled          "   ti,dra746-pcie-ep ti,dra7-pcie-ep           A  Y         axi@1            simple-bus                                   Q  Q    0     0            	  ^disabled       pcie@51800000           =Q      Q    L               rc_dbics ti_conf config               c         d                                    Ipci       0               0               00  0                             ,                       
           pcie2                    
   pcie-phy0           =                     `  P                                                                                             ti,dra746-pcie-rc ti,dra7-pcie          A  Z   interrupt-controller                                   ,           A               ocmcram@40300000          
   mmio-sram           =@0                 @0                                      A  [   sram-hs@0            ti,secure-ram           =                 ocmcram@40400000          	  ^disabled          
   mmio-sram           =@@                 @@                                      A  \      ocmcram@40500000          	  ^disabled          
   mmio-sram           =@P                 @P                                      A  ]      bandgap@4a0021e0          0  =J !   J #,   J #   ,J #   <J %d   J %t   P         ti,dra752-bandgap                  y                      A         dsp_system@40d00000          syscon          =@             A         padconf@4844a000             ti,dra7-iodelay         =HD                                                A  ^   mmc1_iodelay_ddr_conf                     $          0  v      <         H   8      T             K      (          ,          4          8         @          D          L          P          X          \                A  _      mmc1_iodelay_sdr104_conf                 |      (          ,          4          8          @          D          L          P          X          \                A  `      mmc2_iodelay_hs200_conf                     ^               O                S                         &                        d                 C                                 d        h  t            A         mmc3_iodelay_manual1_conf             x          ]                                                                                                                                                              A  a      mmc3_iodelay_sdr50_conf           x  T         ^         z                             [                             9                                                          w                                A  b      mmc4_iodelay_manual1_conf             @          H  {      L  *      P          T          p  u      t          x          |     @                                                   |   ,                            A         mmc4_iodelay_default_conf             @          H          L  3      P          T          p        t          x          |  e                                                        C                                A            dma-controller@4a056000          ti,omap4430-sdma            =J`          0                             	          
           1                       <           dma_system          A         edma@43300000            ti,edma3-tpcc           tpcc            =C0           	  edma3_cc          $        i         h         g         '  edma3_ccint edma3_mperr edma3_ccerrint          <   @        1                                A         tptc@43400000            ti,edma3-tptc           tptc0           =C@                   r           edma3_tcerrint          A         tptc@43500000            ti,edma3-tptc           tptc1           =CP                   s           edma3_tcerrint          A         gpio@4ae10000            ti,omap4-gpio           =J                               gpio1                                        ,           A         gpio@48055000            ti,omap4-gpio           =HP                              gpio2                                        ,           A  c      gpio@48057000            ti,omap4-gpio           =Hp                              gpio3                                        ,           A  d   p1          JCON_LCD_PWR_DN          ?        9                0         gpio@48059000            ti,omap4-gpio           =H                              gpio4                                        ,           A         gpio@4805b000            ti,omap4-gpio           =H                              gpio5                                        ,           A         gpio@4805d000            ti,omap4-gpio           =H                              gpio6                                        ,           A         gpio@48051000            ti,omap4-gpio           =H                              gpio7                                        ,           A         gpio@48053000            ti,omap4-gpio           =H0                   t           gpio8                                        ,           A  e      serial@4806a000          ti,dra742-uart ti,omap4-uart            =H                      C                uart1           el         ^okay                  1      2        tx rx           A  f      serial@4806c000          ti,dra742-uart ti,omap4-uart            =H                   D           uart2           el         ^okay                  3      4        tx rx           A  g      serial@48020000          ti,dra742-uart ti,omap4-uart            =H                    E           uart3           el         ^okay                  5      6        tx rx           A  h      serial@4806e000          ti,dra742-uart ti,omap4-uart            =H                   A           uart4           el       	  ^disabled                  7      8        tx rx           A  i      serial@48066000          ti,dra742-uart ti,omap4-uart            =H`                   d           uart5           el       	  ^disabled                  ?      @        tx rx           A  j      serial@48068000          ti,dra742-uart ti,omap4-uart            =H                   e           uart6           el       	  ^disabled                  O      P        tx rx           A  k      serial@48420000          ti,dra742-uart ti,omap4-uart            =HB                               uart7           el       	  ^disabled            A  l      serial@48422000          ti,dra742-uart ti,omap4-uart            =HB                               uart8           el       	  ^disabled            A  m      serial@48424000          ti,dra742-uart ti,omap4-uart            =HB@                              uart9           el       	  ^disabled            A  n      serial@4ae2b000          ti,dra742-uart ti,omap4-uart            =J                              uart10          el       	  ^disabled            A  o      mailbox@4a0f4000             ti,omap4-mailbox            =J@          $                                      	  mailbox1                       #           5         	  ^disabled            A  p      mailbox@4883a000             ti,omap4-mailbox            =H          0                                                	  mailbox2                       #           5         	  ^disabled            A  q      mailbox@4883c000             ti,omap4-mailbox            =H          0                                                	  mailbox3                       #           5         	  ^disabled            A  r      mailbox@4883e000             ti,omap4-mailbox            =H          0                                                	  mailbox4                       #           5         	  ^disabled            A  s      mailbox@48840000             ti,omap4-mailbox            =H           0                                                	  mailbox5                       #           5           ^okay            A      mbox_ipu1_ipc3x         G                 R                 ^okay            A         mbox_dsp1_ipc3x         G                 R                 ^okay            A            mailbox@48842000             ti,omap4-mailbox            =H           0                                                	  mailbox6                       #           5           ^okay            A      mbox_ipu2_ipc3x         G                 R                 ^okay            A         mbox_dsp2_ipc3x         G                 R                 ^okay            A            mailbox@48844000             ti,omap4-mailbox            =H@          0                                            	  mailbox7                       #           5         	  ^disabled            A  t      mailbox@48846000             ti,omap4-mailbox            =H`          0                                            	  mailbox8                       #           5         	  ^disabled            A  u      mailbox@4885e000             ti,omap4-mailbox            =H          0        	         
                           	  mailbox9                       #           5         	  ^disabled            A  v      mailbox@48860000             ti,omap4-mailbox            =H           0                                            
  mailbox10                      #           5         	  ^disabled            A  w      mailbox@48862000             ti,omap4-mailbox            =H           0                                            
  mailbox11                      #           5         	  ^disabled            A  x      mailbox@48864000             ti,omap4-mailbox            =H@          0                                            
  mailbox12                      #           5         	  ^disabled            A  y      mailbox@48802000             ti,omap4-mailbox            =H           0        {         |         }         ~         
  mailbox13                      #           5         	  ^disabled            A  z      timer@4ae18000           ti,omap5430-timer           =J                               timer1           ]        pfck         i                  A  {      timer@48032000           ti,omap5430-timer           =H                    !           timer2          i   Y   8           pfck         A  |      timer@48034000           ti,omap5430-timer           =H@                   "           timer3          i   Y   @           pfck         A         timer@48036000           ti,omap5430-timer           =H`                   #           timer4          i   Y   H           pfck         A         timer@48820000           ti,omap5430-timer           =H                    $           timer5          i                 pfck         A         timer@48822000           ti,omap5430-timer           =H                    %           timer6          i                  pfck         A         timer@48824000           ti,omap5430-timer           =H@                   &           timer7          i      (           pfck         A         timer@48826000           ti,omap5430-timer           =H`                   '           timer8          i      0           pfck         A         timer@4803e000           ti,omap5430-timer           =H                   (           timer9          i   Y   P           pfck         A         timer@48086000           ti,omap5430-timer           =H`                   )           timer10         i   Y   (           pfck         A         timer@48088000           ti,omap5430-timer           =H                   *           timer11         i   Y   0           pfck         A         timer@4ae20000           ti,omap5430-timer           =J                    Z           timer12          ]         l        i      (           pfck         A  }      timer@48828000           ti,omap5430-timer           =H                  S           timer13         i   Y              pfck         A         timer@4882a000           ti,omap5430-timer           =H                  T           timer14         i   Y              pfck         A  ~      timer@4882c000           ti,omap5430-timer           =H                  U           timer15         i   Y              pfck         A        timer@4882e000           ti,omap5430-timer           =H                  V           timer16         i   Y  0           pfck         A        wdt@4ae14000             ti,omap3-wdt            =J@                   K         
  wd_timer2           A        spinlock@4a0f6000            ti,omap4-hwspinlock         =J`          	  spinlock            |           A        dmm@4e000000             ti,omap5-dmm            =N                     l           dmm       ipu@58820000             ti,dra7-ipu         =X             l2ram           ipu1                       J U         ^okay                                                              A        ipu@55020000             ti,dra7-ipu         =U             l2ram           ipu2                       J          ^okay                                                              A        dsp@40800000             ti,dra7-dsp         =@    @     @             l2ram l1pram l1dram         dsp1               	  \                      J T         ^okay                                                           A        i2c@48070000             ti,omap4-i2c            =H                    3                                     i2c1            ^okay            e         A     tps65917@58          ti,tps65917         =   X                                   ,           A      tps65917_pmic            ti,tps65917-pmic                       +           ;           K           [           j           y                            regulators          A     smps12          smps12          ' P        ?                           A        smps3           smps3           ' P        ?                           A        smps4           smps4           ' P        ?                           A        smps5           smps5           ' w@        ? w@                          A         ldo1            ldo1            ' w@        ? w@                                   A         ldo2            ldo2            ' w@        ? w@                          A        ldo3            ldo3            ' 2Z        ? 2Z                          A         ldo5            ldo5            ' w@        ? w@                          A         ldo4            ldo4            ' w@        ? 2Z                          A               tps65917_power_button            ti,palmas-pwrbutton          &                                               lp87565@60           ti,lp87565-q1           =   `                              A     regulators          A     buck10          buck10          ' P        ?                           A         buck23          buck23          ' P        ?                           A              pcf8757@20           ti,pcf8575 nxp,pcf8575          =                                         ,            &                         A         pcf8757@21           ti,pcf8575 nxp,pcf8575          =   !                             &                                  ,           A         pcf8575@26           ti,pcf8575 nxp,pcf8575          =   &                            A      p1           0        9                ?        Jvin6_sel_s0          tlv320aic3106@19            T             ti,tlv320aic3106            =           e   (        s           ^okay                                                        A            i2c@48072000             ti,omap4-i2c            =H                    4                                     i2c2          	  ^disabled            A        i2c@48060000             ti,omap4-i2c            =H                    8                                     i2c3            ^okay            e         A     pcf8757@20          A                              =   '         ti,pcf8575 nxp,pcf8575    p3          Jls_oe           '        9                0      p2          Jct_hpd          '        9                0            i2c@4807a000             ti,omap4-i2c            =H                   9                                     i2c4          	  ^disabled            A        i2c@4807c000             ti,omap4-i2c            =H                   7                                     i2c5            ^okay            e         A     ov10633@37           ovti,ov10633            =   7        i           pxvclk                                 port       endpoint                                                         A                  mmc@4809c000             ti,dra7-sdhci           =H	                   N           mmc1            ^okay                       q                           *           6           C           M                 Vdefault hs          d           n           A        1w@480b2000          ti,omap3-1w         =H                    5           hdq1w           A        mmc@480b4000             ti,dra7-sdhci           =H@                   Q           mmc2            ^okay            q         x                                          *           6           C                    Vdefault hs ddr_1_8v hs200_1_8v          d           n                                    A        mmc@480ad000             ti,dra7-sdhci           =H
                   Y           mmc3          	  ^disabled            А         x     @          A        mmc@480d1000             ti,dra7-sdhci           =H                   [           mmc4            ^okay            q         x     @          C                                                                *           6           Vdefault hs sdr12 sdr25          d              n                                          A     wifi@2        
   ti,wl1835           =            &                          mmu@40d01000             ti,dra7-dsp-iommu           =@                            
  mmu0_dsp1                                      A         mmu@40d02000             ti,dra7-dsp-iommu           =@                             
  mmu1_dsp1                                     A         mmu@58882000             ti,dra7-iommu           =X                            	  mmu_ipu1                         	        A         mmu@55082000             ti,dra7-iommu           =U                            	  mmu_ipu2                         	        A         pruss-soc-bus@4b226004           ti,am5728-pruss-soc-bus         =K"`           pruss1                                          	  ^disabled            A     pruss@4b200000           ti,am5728-pruss         =K            `                                                                                        0  host2 host3 host4 host5 host6 host7 host8 host9                                         	  ^disabled            A     memories@4b200000           =K       K       K!             dram0 dram1 shrdram2            A        cfg@4b226000             syscon          =K"`             A        iep@4b22e000             syscon          =K"           A        mii-rt@4b232000          syscon          =K#     X        A        interrupt-controller@4b220000            ti,am5728-pruss-intc            =K"                       ,           A         pru@4b234000             ti,am5728-pru           =K#@   0 K"     K"$            iram control debug          	am57xx-pru1_0-fw             &                         vring kick          A        pru@4b238000             ti,am5728-pru           =K#   0 K"@    K"D            iram control debug          	am57xx-pru1_1-fw             &                         vring kick          A        mdio@4b232400            ti,davinci_mdio         =K#$                                      i           pfck         	' B@      	  ^disabled            A              pruss-soc-bus@4b2a6004           ti,am5728-pruss-soc-bus         =K*`           pruss2                                          	  ^disabled            A     pruss@4b280000           ti,am5728-pruss         =K(           `                                                                                        0  host2 host3 host4 host5 host6 host7 host8 host9                                         	  ^disabled            A     memories@4b280000           =K(      K(      K)             dram0 dram1 shrdram2            A        cfg@4b2a6000             syscon          =K*`             A        iep@4b2ae000             syscon          =K*           A        mii-rt@4b2b2000          syscon          =K+     X        A        interrupt-controller@4b2a0000            ti,am5728-pruss-intc            =K*                       ,           A         pru@4b2b4000             ti,am5728-pru           =K+@   0 K*     K*$            iram control debug          	am57xx-pru2_0-fw             &                         vring kick          A        pru@4b2b8000             ti,am5728-pru           =K+   0 K*@    K*D            iram control debug          	am57xx-pru2_1-fw             &                         vring kick          A        mdio@4b2b2400            ti,davinci_mdio         =K+$                                      i           pfck         	' B@      	  ^disabled            A              regulator-abb-mpu         
   ti,abb-v3           abb_mpu                                    i           	0   2        	A         (  =J}   J}   J`   J ;    JX         D  setup-address control-address int-address efuse-address ldo-address         	Q           	j           	         `  	 ,                  @                 v                                         A         regulator-abb-ivahd       
   ti,abb-v3         
  abb_ivahd                                      i           	0   2        	A         (  =J~4   J~$   J`   J %   J $p         D  setup-address control-address int-address efuse-address ldo-address         	Q@           	j           	         H  	                   0                                         A        regulator-abb-dspeve          
   ti,abb-v3           abb_dspeve                                     i           	0   2        	A         (  =J~0   J~    J`   J %   J $l         D  setup-address control-address int-address efuse-address ldo-address         	Q            	j           	         H  	                   0                                         A        regulator-abb-gpu         
   ti,abb-v3           abb_gpu                                    i           	0   2        	A         (  =J}   J}   J`   J ;   JT         D  setup-address control-address int-address efuse-address ldo-address         	Q           	j           	         H  	                   v                                          A        spi@48098000             ti,omap4-mcspi          =H	                   <                                     mcspi1          	         @        #      $      %      &      '      (      )      *         tx0 rx0 tx1 rx1 tx2 rx2 tx3 rx3         ^okay            A        spi@4809a000             ti,omap4-mcspi          =H	                   =                                     mcspi2          	                  +      ,      -      .        tx0 rx0 tx1 rx1         ^okay            A        spi@480b8000             ti,omap4-mcspi          =H                   V                                     mcspi3          	                               tx0 rx0       	  ^disabled            A        spi@480ba000             ti,omap4-mcspi          =H                   +                                     mcspi4          	                 F      G        tx0 rx0       	  ^disabled            A        qspi@4b300000            ti,dra7xxx-qspi         =K0     \              qspi_base qspi_mmap         	   	  X                                  qspi            i   Y  8           pfck         	                 W           ^okay            	         A     m25p80@0             s25fl256s1          	         =            	           	                               partition@0       	  	QSPI.SPL            =             partition@1         	QSPI.SPL.backup1            =            partition@2         	QSPI.SPL.backup2            =            partition@3         	QSPI.SPL.backup3            =            partition@4         	QSPI.u-boot         =            partition@5         	QSPI.u-boot-spl-os          =            partition@6         	QSPI.u-boot-env         =            partition@7         	QSPI.u-boot-env.backup1         =            partition@8         	QSPI.kernel         =            partition@9         	QSPI.file-system            =   b              ocp2scp@4a090000             ti,omap-ocp2scp                                           =J	            	  ocp2scp3       phy@4a096000             ti,phy-pipe3-sata           =J	`    J	d    dJ	h    @        phy_rx phy_tx pll_ctrl          	   	  t        i         h           psysclk refclk           
   	          
            A         pciephy@4a094000             ti,phy-pipe3-pcie           =J	@    J	D    d        phy_rx phy_tx           	              
)            4  i   @   A                  	         
            ;  pdpll_ref dpll_ref_m2 wkupclk refclk div-clk phy-div sysclk          
            A         pciephy@4a095000             ti,phy-pipe3-pcie           =J	P    J	T    d        phy_rx phy_tx           	               
)            4  i   @   A                  	         
            ;  pdpll_ref dpll_ref_m2 wkupclk refclk div-clk phy-div sysclk          
            ^okay            A            sata@4a141100            snps,dwc-ahci           =J     J                   1                    	   sata-phy            i      h           sata            
4           A        rtc@48838000             ti,am3352-rtc           =H                                        rtcss           i   R      	  ^disabled            A        ocp2scp@4a080000             ti,omap-ocp2scp                                           =J            	  ocp2scp1       phy@4a084000             ti,dra7x-usb2 ti,omap-usb2          =J@            	   	           i                    pwkupclk refclk          
            
F           A         phy@4a085000              ti,dra7x-usb2-phy2 ti,omap-usb2         =JP            	   	  t        i                     pwkupclk refclk          
            
F           A         phy@4a084400             ti,omap-usb3            =JD    JH    dJL    @        phy_rx phy_tx pll_ctrl          	   	  p        i                       pwkupclk sysclk refclk           
            A            target-module@4a0dd000           ti,sysc-omap4-sr ti,sysc            smartreflex_core            =J8           sysc            
Q           
^                     i                  pfck                                      J          target-module@4a0d9000           ti,sysc-omap4-sr ti,sysc            smartreflex_mpu         =J8           sysc            
Q           
^                     i                  pfck                                      J          omap_dwc3_1@48880000             ti,dwc3         usb_otg_ss1         =H                    H                                    
l                    
v           A     usb@48890000          
   snps,dwc3           =H   p       $         G          G          H           peripheral host otg                        usb2-phy usb3-phy           
}super-speed         
otg          
         
        
v           A           omap_dwc3_2@488c0000             ti,dwc3         usb_otg_ss2         =H                    W                                    
l                    
v           A     usb@488d0000          
   snps,dwc3           =H   p       $         I          I          W           peripheral host otg                  	   usb2-phy            
}high-speed          
host             
         
         
        
v           A           omap_dwc3_3@48900000             ti,dwc3         usb_otg_ss3         =H                   X                                    
l                  	  ^disabled            A     usb@48910000          
   snps,dwc3           =H   p       $         X          X         X           peripheral host otg         
}high-speed          
otg          
         
        A           elm@48078000             ti,am3352-elm           =H                             elm       	  ^disabled            A        gpmc@50000000            ti,am3352-gpmc          gpmc            =P     |                                            rxtx            
           
                                             ,                             	  ^disabled            A        atl@4843c000             ti,dra7-atl         =HC           atl                              i                  pfck         ^okay               c                              b   f                
@   V"         A     atl2                                   mcasp@48460000           ti,dra7-mcasp-audio         mcasp1          =HF      E             mpu dat                h          g           tx rx                                     tx rx         $  i                                   pfck ahclkx ahclkr         	  ^disabled            A        mcasp@48464000           ti,dra7-mcasp-audio         mcasp2          =HF@     E             mpu dat                                     tx rx                                     tx rx         $  i   Y  `      Y  `      Y  `           pfck ahclkx ahclkr         	  ^disabled            A        mcasp@48468000           ti,dra7-mcasp-audio         mcasp3          =HF     F              mpu dat                                     tx rx                                     tx rx           i   Y  h      Y  h           pfck ahclkx          ^okay            T               Y  h                                  #           -                      8            C            A         mcasp@4846c000           ti,dra7-mcasp-audio         mcasp4          =HF     HC`            mpu dat                                     tx rx                                     tx rx           i   Y        Y             pfck ahclkx        	  ^disabled            A        mcasp@48470000           ti,dra7-mcasp-audio         mcasp5          =HG      HC            mpu dat                                     tx rx                                     tx rx           i   Y  x      Y  x           pfck ahclkx        	  ^disabled            A        mcasp@48474000           ti,dra7-mcasp-audio         mcasp6          =HG@     HD            mpu dat                                     tx rx                                     tx rx           i   Y        Y             pfck ahclkx        	  ^disabled            A        mcasp@48478000           ti,dra7-mcasp-audio         mcasp7          =HG     HE             mpu dat                                     tx rx                                     tx rx           i   Y        Y             pfck ahclkx        	  ^disabled            A        mcasp@4847c000           ti,dra7-mcasp-audio         mcasp8          =HG     HE@            mpu dat                                     tx rx                                     tx rx           i   Y        Y             pfck ahclkx        	  ^disabled            A        crossbar@4a002a48            ti,irq-crossbar         =J *H  0                  &           ,           N           Z          r            ~                                    
   C   D                             A         ethernet@48484000            ti,dra7-cpsw ti,cpsw            gmac            i                  	  pfck cpts                                                                                 xL                   =HH@    HHR   .                                         0        N         O         P         Q                       	        ^okay                      A     mdio@48485000            ti,cpsw-mdio ti,davinci_mdio                                      davinci_mdio            	' B@        =HHP            A      ethernet-phy@2          =           *           ?            T            b         z        A        ethernet-phy@3          =           *           ?            T            b         z        A           slave@48480200                                      	  rgmii-id                       A        slave@48480300                                      	  rgmii-id                       A        cpsw-phy-sel@4a002554            ti,dra7xx-cpsw-phy-sel          =J %T         	  gmii-sel            A           can@4ae3c000             ti,dra7-d_can           dcan1           =J                	  X                              i      h         	  ^disabled            A        can@48480000             ti,dra7-d_can           dcan2           =HH                 	  X                             i         	  ^disabled            A        gpu@56000000             ti,dra7-sgx544 img,sgx544           =V              gpu_ocp_base                              gpu         i   
   U   V        piclk fclk1 fclk2            ^ok          A        bb2d@59000000            ti,dra7-bb2d            =Y                     x           bb2d            i                  pfck       	  ^disabled            A        dss@58000000             ti,dra7-dss         ^ok        	  dss_core               	  8                                        (  =X      X @T   X C     X T   X            (  dss pll1_clkctrl pll1 pll2_clkctrl pll2       $  i                                      pfck video1_clk video2_clk                      A     ports           ^ok                               port            =       endpoint            A          '                         dispc@58001000           ti,dra7-dispc           =X                             
  dss_dispc           i                  pfck            	  4      encoder@58060000             ti,dra7-hdmi             =X     X    X    X            wp pll phy core                `           ^ok        	  dss_hdmi            i          	          
        pfck sys_clk               L      	  audio_tx                       A     port       endpoint                       A                  epwmss@4843e000           ti,dra746-pwmss ti,am33xx-pwmss         =HC    0        epwmss0                                	  ^disabled                     A     pwm@4843e200          "   ti,dra746-ehrpwm ti,am3352-ehrpwm                      =HC            i            
  ptbclk fck         	  ^disabled            A        ecap@4843e100            ti,dra746-ecap ti,am3352-ecap                      =HC            i           pfck       	  ^disabled            A           epwmss@48440000           ti,dra746-pwmss ti,am33xx-pwmss         =HD     0        epwmss1                                	  ^disabled                     A     pwm@48440200          "   ti,dra746-ehrpwm ti,am3352-ehrpwm                      =HD            i            
  ptbclk fck         	  ^disabled            A        ecap@48440100            ti,dra746-ecap ti,am3352-ecap                      =HD            i           pfck       	  ^disabled            A           epwmss@48442000           ti,dra746-pwmss ti,am33xx-pwmss         =HD     0        epwmss2                                	  ^disabled                     A     pwm@48442200          "   ti,dra746-ehrpwm ti,am3352-ehrpwm                      =HD"            i            
  ptbclk fck         	  ^disabled            A        ecap@48442100            ti,dra746-ecap ti,am3352-ecap                      =HD!            i           pfck       	  ^disabled            A           aes@4b500000             ti,omap4-aes            aes1            =KP                    P                 o          n            tx rx           i   
        pfck         A        aes@4b700000             ti,omap4-aes            aes2            =Kp                    ;                 r          q            tx rx           i   
        pfck         A        des@480a5000             ti,omap4-des            des         =H
P                   M                 u      t        tx rx           i   
        pfck         A        sham@53100000            ti,omap5-sham           sham            =K                   .                 w            rx          i   
        pfck         A        rng@48090000             ti,omap4-rng            rng         =H	                     /           i   
        pfck         A        opp-supply@4a003b20          ti,omap5-opp-supply         =J ;              ,     @    v               , `        A        vpe          ti,vpe          vpe         i   X        pfck          =H     H    HW    H            vpe_top sc csc vpdma                  b                                   vip@0x48970000           ti,vip1       @  =H    HU    HW    HX    HZ    H\    H]    H          ,  vip parser0 csc0 sc0 parser1 csc1 sc1 vpdma         vip1                  _                       	  4                                  ^okay            A     ports                                port@0          =            A        port@1          =           A     endpoint@0           G                   A            port@2          =           A        port@3          =           A              dsp_system@41500000          syscon          =AP             A         omap_dwc3_4@48940000             ti,dwc3         usb_otg_ss4         =H                   Z                                    
l                  	  ^disabled            A     usb@48950000          
   snps,dwc3           =H   p       $        Y         Y         Z           peripheral host otg         
}high-speed          
otg         A           mmu@41501000             ti,dra7-dsp-iommu           =AP                            
  mmu0_dsp2                                      A         mmu@41502000             ti,dra7-dsp-iommu           =AP                             
  mmu1_dsp2                                     A         dsp@41000000             ti,dra7-dsp         =A     A`     Ap             l2ram l1pram l1dram         dsp2               	  `                      J V         ^okay                                                           A        vip@0x48990000           ti,vip2       @  =H    HU    HW    HX    HZ    H\    H]    H          ,  vip parser0 csc0 sc0 parser1 csc1 sc1 vpdma         vip2                  `                       	  4                                	  ^disabled            A     ports                                port@0          =            A        port@1          =           A        port@2          =           A        port@3          =           A              vip@0x489b0000           ti,vip3       @  =H    HU    HW    HX    HZ    H\    H]    H          ,  vip parser0 csc0 sc0 parser1 csc1 sc1 vpdma         vip3                  a                       	  4                                	  ^disabled            A     ports                                port@0          =            A        port@1          =           A              emif@4c000000            ti,emif-dra7xx          =L                     i         	  ^disabled            A        target-module@42c01900           ti,sysc-dra7-mcan ti,sysc               B                                       =B    B   B           rev sysc syss           
Q           R           i                  pfck    mcan@1a00            bosch,m_can         =     @               m_can message_ram            &                  C          D         
  int0 int1           i      
      
  pcclk hclk            _                                      A     can-transceiver         n LK@            cal@489b0000             ti,dra76-cal            cal         =H     H    @H	    @      "  cal_top cal_rx_core0 cal_rx_core1                 a           z   	                                  	  ^disabled            A     ports                                port@0          =            A        port@1          =           A                 thermal-zones           A     cpu_thermal                                                           A     trips           A     cpu_alert                              Ppassive         A         cpu_crit                             	  Pcritical            A           cooling-maps            A     map0                                      gpu_thermal                                                          A     trips      gpu_crit                             	  Pcritical            A              core_thermal                                                             A     trips      core_crit                            	  Pcritical            A              dspeve_thermal                                                           A     trips      dspeve_crit                          	  Pcritical            A              iva_thermal                                                          A     trips      iva_crit                             	  Pcritical            A                  pmu          arm,cortex-a15-pmu           &                                     extcon_usb1          linux,extcon-usb-gpio                                               A         extcon_usb2          linux,extcon-usb-gpio                                               A         sound0           simple-audio-card           DRA7xx-EVM        H  Headphone Headphone Jack Line Line Out Microphone Mic Jack Line Line In         8Headphone Jack HPLOUT Headphone Jack HPROUT Line Out LLOUT Line Out RLOUT MIC3L Mic Jack MIC3R Mic Jack Mic Jack Mic Bias LINE1L Line In LINE1R Line In         Rdsp_b           k                               A     simple-audio-card,cpu                       V"         A         simple-audio-card,codec                    i            leds          
   gpio-leds      led0          
  	dra7:usr1           9                 off       led1          
  	dra7:usr2           9                 off       led2          
  	dra7:usr3           9                 off       led3          
  	dra7:usr4           9                 off          gpio_keys         
   gpio-keys                                          USER1         	  	btnUser1                       9               USER2         	  	btnUser2                      9                  clk_ov10633_fixed           W             fixed-clock         en6         A         memory@0            Imemory          =                    reserved-memory                                      ipu2_cma@95800000            shared-dma-pool         =                             ^okay            A         dsp1_cma@99000000            shared-dma-pool         =                               ^okay            A         ipu1_cma@9d000000            shared-dma-pool         =                               ^okay            A         dsp2_cma@9f000000            shared-dma-pool         =                               ^okay            A            fixedregulator-vsys12v0          regulator-fixed       
  vsys_12v0           '          ?                            A         fixedregulator-vsys5v0           regulator-fixed       	  vsys_5v0            ' LK@        ? LK@                                     A         fixedregulator-vio_3v6           regulator-fixed         vio_3v6         ' 6        ? 6                                     A         fixedregulator-vsys3v3           regulator-fixed       	  vsys_3v3            ' 2Z        ? 2Z                                     A         fixedregulator-vio_3v3           regulator-fixed         vio_3v3         ' 2Z        ? 2Z                                     A         fixedregulator-sd            regulator-fixed         vio_3v3_sd          ' 2Z        ? 2Z                    *                          A         fixedregulator-vio_1v8           regulator-fixed         vio_1v8         ' w@        ? w@                   A         fixedregulator-mmcwl             regulator-fixed         vmmcwl_fixed            ' w@        ? w@                          = p         *        A         fixedregulator-vtt           regulator-fixed       
  vtt_fixed           ' p        ? p                                     A        fixedregulator-aic_dvdd          regulator-fixed       	  aic_dvdd                       ' w@        ? w@        A         connector            hdmi-connector          	hdmi            Pa           A     port       endpoint                       A               encoder          ti,tpd12s015          $  9                                      A     ports                                port@0          =       endpoint                       A            port@1          =      endpoint                       A                  __symbols__         '/ocp/i2c@48060000/pcf8757@20  nd      '  '/ocp/dss@58000000/ports/port/endpoint          '/connector@0/port/endpoint          '/connector@0  ts      $  '/encoder@0/ports/port@1/endpoint@0        $  '/encoder@0/ports/port@0/endpoint@0          '/encoder@0          N/interrupt-controller@48211000          R/interrupt-controller@48281000          \/cpus/cpu@0         a/opp-table          p/ocp/l4@4a000000            w/ocp/l4@4a000000/scm@2000         %  {/ocp/l4@4a000000/scm@2000/scm_conf@0          9  /ocp/l4@4a000000/scm@2000/scm_conf@0/pbias_regulator@e00          I  /ocp/l4@4a000000/scm@2000/scm_conf@0/pbias_regulator@e00/pbias_mmc_omap5          ,  /ocp/l4@4a000000/scm@2000/scm_conf@0/clocks       @  /ocp/l4@4a000000/scm@2000/scm_conf@0/clocks/dss_deshdcp_clk@558       >  /ocp/l4@4a000000/scm@2000/scm_conf@0/clocks/ehrpwm0_tbclk@558         >  /ocp/l4@4a000000/scm@2000/scm_conf@0/clocks/ehrpwm1_tbclk@558         >  /ocp/l4@4a000000/scm@2000/scm_conf@0/clocks/ehrpwm2_tbclk@558         7  /ocp/l4@4a000000/scm@2000/scm_conf@0/clocks/sys_32k_ck        H  /ocp/l4@4a000000/scm@2000/scm_conf@0/clocks/dpll_gmac_h14x2_ctrl_ck@3fc       L  /ocp/l4@4a000000/scm@2000/scm_conf@0/clocks/dpll_gmac_h14x2_ctrl_mux_ck@3fc       9  +/ocp/l4@4a000000/scm@2000/scm_conf@0/clocks/mcan_clk@3fc          &  4/ocp/l4@4a000000/scm@2000/pinmux@1400         8  B/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc1_pins_default       3  T/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc1_pins_hs        6  a/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc1_pins_sdr50         6  q/ocp/l4@4a000000/scm@2000/pinmux@1400/mmc1_pins_ddr50         8  /ocp/l4@4a000000/scm@2000/pinmux@1400/mmc2_pins_default       6  /ocp/l4@4a000000/scm@2000/pinmux@1400/mmc2_pins_hs200         8  /ocp/l4@4a000000/scm@2000/pinmux@1400/mmc3_pins_default       3  /ocp/l4@4a000000/scm@2000/pinmux@1400/mmc4_pins_hs        (  /ocp/l4@4a000000/scm@2000/scm_conf@1c04       (  /ocp/l4@4a000000/scm@2000/scm_conf@1c24       )  /ocp/l4@4a000000/scm@2000/dma-router@b78          )  /ocp/l4@4a000000/scm@2000/dma-router@c78          "  /ocp/l4@4a000000/cm_core_aon@5000         )  /ocp/l4@4a000000/cm_core_aon@5000/clocks          7  /ocp/l4@4a000000/cm_core_aon@5000/clocks/atl_clkin0_ck        7  /ocp/l4@4a000000/cm_core_aon@5000/clocks/atl_clkin1_ck        7  )/ocp/l4@4a000000/cm_core_aon@5000/clocks/atl_clkin2_ck        7  7/ocp/l4@4a000000/cm_core_aon@5000/clocks/atl_clkin3_ck        7  E/ocp/l4@4a000000/cm_core_aon@5000/clocks/hdmi_clkin_ck        6  S/ocp/l4@4a000000/cm_core_aon@5000/clocks/mlb_clkin_ck         7  `/ocp/l4@4a000000/cm_core_aon@5000/clocks/mlbp_clkin_ck        =  n/ocp/l4@4a000000/cm_core_aon@5000/clocks/pciesref_acs_clk_ck          7  /ocp/l4@4a000000/cm_core_aon@5000/clocks/ref_clkin0_ck        7  /ocp/l4@4a000000/cm_core_aon@5000/clocks/ref_clkin1_ck        7  /ocp/l4@4a000000/cm_core_aon@5000/clocks/ref_clkin2_ck        7  /ocp/l4@4a000000/cm_core_aon@5000/clocks/ref_clkin3_ck        5  /ocp/l4@4a000000/cm_core_aon@5000/clocks/rmii_clk_ck          9  /ocp/l4@4a000000/cm_core_aon@5000/clocks/sdvenc_clkin_ck          ?  /ocp/l4@4a000000/cm_core_aon@5000/clocks/secure_32k_clk_src_ck        >  /ocp/l4@4a000000/cm_core_aon@5000/clocks/sys_clk32_crystal_ck         =  /ocp/l4@4a000000/cm_core_aon@5000/clocks/sys_clk32_pseudo_ck          :  /ocp/l4@4a000000/cm_core_aon@5000/clocks/virt_12000000_ck         :  &/ocp/l4@4a000000/cm_core_aon@5000/clocks/virt_13000000_ck         :  7/ocp/l4@4a000000/cm_core_aon@5000/clocks/virt_16800000_ck         :  H/ocp/l4@4a000000/cm_core_aon@5000/clocks/virt_19200000_ck         :  Y/ocp/l4@4a000000/cm_core_aon@5000/clocks/virt_20000000_ck         :  j/ocp/l4@4a000000/cm_core_aon@5000/clocks/virt_26000000_ck         :  {/ocp/l4@4a000000/cm_core_aon@5000/clocks/virt_27000000_ck         :  /ocp/l4@4a000000/cm_core_aon@5000/clocks/virt_38400000_ck         4  /ocp/l4@4a000000/cm_core_aon@5000/clocks/sys_clkin2       :  /ocp/l4@4a000000/cm_core_aon@5000/clocks/usb_otg_clkin_ck         9  /ocp/l4@4a000000/cm_core_aon@5000/clocks/video1_clkin_ck          <  /ocp/l4@4a000000/cm_core_aon@5000/clocks/video1_m2_clkin_ck       9  /ocp/l4@4a000000/cm_core_aon@5000/clocks/video2_clkin_ck          <  /ocp/l4@4a000000/cm_core_aon@5000/clocks/video2_m2_clkin_ck       9  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_abe_ck@1e0          8  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_abe_x2_ck       >  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_abe_m2x2_ck@1f0         5  +/ocp/l4@4a000000/cm_core_aon@5000/clocks/abe_clk@108          <  3/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_abe_m2_ck@1f0       >  B/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_abe_m3x2_ck@1f4         ?  S/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_byp_mux@12c        :  e/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_ck@120         9  r/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_x2_ck          @  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_h12x2_ck@13c       =  /ocp/l4@4a000000/cm_core_aon@5000/clocks/mpu_dpll_hs_clk_div          9  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_mpu_ck@160          <  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_mpu_m2_ck@170       6  /ocp/l4@4a000000/cm_core_aon@5000/clocks/mpu_dclk_div         =  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dsp_dpll_hs_clk_div          >  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_dsp_byp_mux@240         9  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_dsp_ck@234          <  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_dsp_m2_ck@244       =  /ocp/l4@4a000000/cm_core_aon@5000/clocks/iva_dpll_hs_clk_div          >  %/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_iva_byp_mux@1ac         9  6/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_iva_ck@1a0          <  B/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_iva_m2_ck@1b0       2  Q/ocp/l4@4a000000/cm_core_aon@5000/clocks/iva_dclk         >  Z/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gpu_byp_mux@2e4         9  k/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gpu_ck@2d8          <  w/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gpu_m2_ck@2e8       =  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_m2_ck@130          @  /ocp/l4@4a000000/cm_core_aon@5000/clocks/core_dpll_out_dclk_div       >  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_ddr_byp_mux@21c         9  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_ddr_ck@210          <  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_ddr_m2_ck@220       ?  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gmac_byp_mux@2b4        :  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gmac_ck@2a8         =  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gmac_m2_ck@2b8          9  /ocp/l4@4a000000/cm_core_aon@5000/clocks/video2_dclk_div          9  /ocp/l4@4a000000/cm_core_aon@5000/clocks/video1_dclk_div          7  (/ocp/l4@4a000000/cm_core_aon@5000/clocks/hdmi_dclk_div        =  6/ocp/l4@4a000000/cm_core_aon@5000/clocks/per_dpll_hs_clk_div          =  J/ocp/l4@4a000000/cm_core_aon@5000/clocks/usb_dpll_hs_clk_div          =  ^/ocp/l4@4a000000/cm_core_aon@5000/clocks/eve_dpll_hs_clk_div          >  r/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_eve_byp_mux@290         9  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_eve_ck@284          <  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_eve_m2_ck@294       6  /ocp/l4@4a000000/cm_core_aon@5000/clocks/eve_dclk_div         @  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_h13x2_ck@140       @  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_h14x2_ck@144       @  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_h22x2_ck@154       @  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_h23x2_ck@158       @  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_core_h24x2_ck@15c       8  
/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_ddr_x2_ck       ?  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_ddr_h11x2_ck@228        8  +/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_dsp_x2_ck       >  :/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_dsp_m3x2_ck@248         9  K/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gmac_x2_ck          @  [/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gmac_h11x2_ck@2c0       @  n/ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gmac_h12x2_ck@2c4       @  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gmac_h13x2_ck@2c8       ?  /ocp/l4@4a000000/cm_core_aon@5000/clocks/dpll_gmac_m3x2_ck@2bc        8  /ocp/l4@4a000000/cm_core_aon@5000/clocks/gmii_m_clk_div       7  /ocp/l4@4a000000/cm_core_aon@5000/clocks/hdmi_clk2_div        6  /ocp/l4@4a000000/cm_core_aon@5000/clocks/hdmi_div_clk         9  /ocp/l4@4a000000/cm_core_aon@5000/clocks/l3_iclk_div@100          9  /ocp/l4@4a000000/cm_core_aon@5000/clocks/l4_root_clk_div          9  /ocp/l4@4a000000/cm_core_aon@5000/clocks/video1_clk2_div          8  /ocp/l4@4a000000/cm_core_aon@5000/clocks/video1_div_clk       9  /ocp/l4@4a000000/cm_core_aon@5000/clocks/video2_clk2_div          8  /ocp/l4@4a000000/cm_core_aon@5000/clocks/video2_div_clk       2  */ocp/l4@4a000000/cm_core_aon@5000/clocks/dummy_ck         /  3/ocp/l4@4a000000/cm_core_aon@5000/clockdomains        -  L/ocp/l4@4a000000/cm_core_aon@5000/mpu_cm@300          4  S/ocp/l4@4a000000/cm_core_aon@5000/mpu_cm@300/clk@20       .  _/ocp/l4@4a000000/cm_core_aon@5000/dsp1_cm@400         5  g/ocp/l4@4a000000/cm_core_aon@5000/dsp1_cm@400/clk@20          .  t/ocp/l4@4a000000/cm_core_aon@5000/ipu1_cm@500         5  |/ocp/l4@4a000000/cm_core_aon@5000/ipu1_cm@500/clk@20          -  /ocp/l4@4a000000/cm_core_aon@5000/ipu_cm@540          3  /ocp/l4@4a000000/cm_core_aon@5000/ipu_cm@540/clk@0        .  /ocp/l4@4a000000/cm_core_aon@5000/dsp2_cm@600         5  /ocp/l4@4a000000/cm_core_aon@5000/dsp2_cm@600/clk@20          -  /ocp/l4@4a000000/cm_core_aon@5000/rtc_cm@700          4  /ocp/l4@4a000000/cm_core_aon@5000/rtc_cm@700/clk@40         /ocp/l4@4a000000/cm_core@8000         %  /ocp/l4@4a000000/cm_core@8000/clocks          :  /ocp/l4@4a000000/cm_core@8000/clocks/dpll_pcie_ref_ck@200         @  /ocp/l4@4a000000/cm_core@8000/clocks/dpll_pcie_ref_m2ldo_ck@210       C  /ocp/l4@4a000000/cm_core@8000/clocks/apll_pcie_in_clk_mux@4ae06118        6  /ocp/l4@4a000000/cm_core@8000/clocks/apll_pcie_ck@21c         B  %/ocp/l4@4a000000/cm_core@8000/clocks/optfclk_pciephy_div@4a00821c         9  9/ocp/l4@4a000000/cm_core@8000/clocks/apll_pcie_clkvcoldo          =  M/ocp/l4@4a000000/cm_core@8000/clocks/apll_pcie_clkvcoldo_div          5  e/ocp/l4@4a000000/cm_core@8000/clocks/apll_pcie_m2_ck          :  u/ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_byp_mux@14c         5  /ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_ck@140          8  /ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_m2_ck@150       ;  /ocp/l4@4a000000/cm_core@8000/clocks/func_96m_aon_dclk_div        :  /ocp/l4@4a000000/cm_core@8000/clocks/dpll_usb_byp_mux@18c         5  /ocp/l4@4a000000/cm_core@8000/clocks/dpll_usb_ck@180          8  /ocp/l4@4a000000/cm_core@8000/clocks/dpll_usb_m2_ck@190       =  /ocp/l4@4a000000/cm_core@8000/clocks/dpll_pcie_ref_m2_ck@210          4  /ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_x2_ck       ;  /ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_h11x2_ck@158        ;  /ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_h12x2_ck@15c        ;  */ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_h13x2_ck@160        ;  </ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_h14x2_ck@164        :  N/ocp/l4@4a000000/cm_core@8000/clocks/dpll_per_m2x2_ck@150         8  _/ocp/l4@4a000000/cm_core@8000/clocks/dpll_usb_clkdcoldo       3  r/ocp/l4@4a000000/cm_core@8000/clocks/func_128m_clk        3  /ocp/l4@4a000000/cm_core@8000/clocks/func_12m_fclk        2  /ocp/l4@4a000000/cm_core@8000/clocks/func_24m_clk         3  /ocp/l4@4a000000/cm_core@8000/clocks/func_48m_fclk        3  /ocp/l4@4a000000/cm_core@8000/clocks/func_96m_fclk        9  /ocp/l4@4a000000/cm_core@8000/clocks/l3init_60m_fclk@104          5  /ocp/l4@4a000000/cm_core@8000/clocks/clkout2_clk@6b0          ;  /ocp/l4@4a000000/cm_core@8000/clocks/l3init_960m_gfclk@6c0        C  /ocp/l4@4a000000/cm_core@8000/clocks/usb_phy1_always_on_clk32k@640        C  /ocp/l4@4a000000/cm_core@8000/clocks/usb_phy2_always_on_clk32k@688        C  /ocp/l4@4a000000/cm_core@8000/clocks/usb_phy3_always_on_clk32k@698        <  3/ocp/l4@4a000000/cm_core@8000/clocks/gpu_core_gclk_mux@1220       ;  E/ocp/l4@4a000000/cm_core@8000/clocks/gpu_hyd_gclk_mux@1220        =  V/ocp/l4@4a000000/cm_core@8000/clocks/l3instr_ts_gclk_div@e50          8  j/ocp/l4@4a000000/cm_core@8000/clocks/vip1_gclk_mux@1020       8  x/ocp/l4@4a000000/cm_core@8000/clocks/vip2_gclk_mux@1028       8  /ocp/l4@4a000000/cm_core@8000/clocks/vip3_gclk_mux@1030       +  /ocp/l4@4a000000/cm_core@8000/clockdomains        9  /ocp/l4@4a000000/cm_core@8000/clockdomains/coreaon_clkdm          -  /ocp/l4@4a000000/cm_core@8000/coreaon_cm@600          4  /ocp/l4@4a000000/cm_core@8000/coreaon_cm@600/clk@20       -  /ocp/l4@4a000000/cm_core@8000/l3main1_cm@700          4  /ocp/l4@4a000000/cm_core@8000/l3main1_cm@700/clk@20       *  /ocp/l4@4a000000/cm_core@8000/ipu2_cm@900         1  /ocp/l4@4a000000/cm_core@8000/ipu2_cm@900/clk@20          )  /ocp/l4@4a000000/cm_core@8000/dma_cm@a00          0  	/ocp/l4@4a000000/cm_core@8000/dma_cm@a00/clk@20       *  /ocp/l4@4a000000/cm_core@8000/emif_cm@b00         1  /ocp/l4@4a000000/cm_core@8000/emif_cm@b00/clk@20          )  */ocp/l4@4a000000/cm_core@8000/atl_cm@c00          /  1/ocp/l4@4a000000/cm_core@8000/atl_cm@c00/clk@0        +  =/ocp/l4@4a000000/cm_core@8000/l4cfg_cm@d00        2  F/ocp/l4@4a000000/cm_core@8000/l4cfg_cm@d00/clk@20         -  T/ocp/l4@4a000000/cm_core@8000/l3instr_cm@e00          4  _/ocp/l4@4a000000/cm_core@8000/l3instr_cm@e00/clk@20       *  o/ocp/l4@4a000000/cm_core@8000/dss_cm@1100         1  v/ocp/l4@4a000000/cm_core@8000/dss_cm@1100/clk@20          -  /ocp/l4@4a000000/cm_core@8000/l3init_cm@1300          4  /ocp/l4@4a000000/cm_core@8000/l3init_cm@1300/clk@20       ,  /ocp/l4@4a000000/cm_core@8000/l4per_cm@1700       2  /ocp/l4@4a000000/cm_core@8000/l4per_cm@1700/clk@0           /ocp/l4@4ae00000            /ocp/l4@4ae00000/counter@4000           /ocp/l4@4ae00000/prm@6000         !  /ocp/l4@4ae00000/prm@6000/clocks          0  /ocp/l4@4ae00000/prm@6000/clocks/sys_clkin1@110       :  /ocp/l4@4ae00000/prm@6000/clocks/abe_dpll_sys_clk_mux@118         =  /ocp/l4@4ae00000/prm@6000/clocks/abe_dpll_bypass_clk_mux@114          6  /ocp/l4@4ae00000/prm@6000/clocks/abe_dpll_clk_mux@10c         2  /ocp/l4@4ae00000/prm@6000/clocks/abe_24m_fclk@11c         /  */ocp/l4@4ae00000/prm@6000/clocks/aess_fclk@178        3  4/ocp/l4@4ae00000/prm@6000/clocks/abe_giclk_div@174        4  B/ocp/l4@4ae00000/prm@6000/clocks/abe_lp_clk_div@1d8       5  Q/ocp/l4@4ae00000/prm@6000/clocks/abe_sys_clk_div@120          3  a/ocp/l4@4ae00000/prm@6000/clocks/adc_gfclk_mux@1dc        7  o/ocp/l4@4ae00000/prm@6000/clocks/sys_clk1_dclk_div@1c8        7  /ocp/l4@4ae00000/prm@6000/clocks/sys_clk2_dclk_div@1cc        9  /ocp/l4@4ae00000/prm@6000/clocks/per_abe_x1_dclk_div@1bc          2  /ocp/l4@4ae00000/prm@6000/clocks/dsp_gclk_div@18c         .  /ocp/l4@4ae00000/prm@6000/clocks/gpu_dclk@1a0         7  /ocp/l4@4ae00000/prm@6000/clocks/emif_phy_dclk_div@190        8  /ocp/l4@4ae00000/prm@6000/clocks/gmac_250m_dclk_div@19c       /  /ocp/l4@4ae00000/prm@6000/clocks/gmac_main_clk        :  /ocp/l4@4ae00000/prm@6000/clocks/l3init_480m_dclk_div@1ac         6  /ocp/l4@4ae00000/prm@6000/clocks/usb_otg_dclk_div@184         3  /ocp/l4@4ae00000/prm@6000/clocks/sata_dclk_div@1c0        4  $/ocp/l4@4ae00000/prm@6000/clocks/pcie2_dclk_div@1b8       3  3/ocp/l4@4ae00000/prm@6000/clocks/pcie_dclk_div@1b4        2  A/ocp/l4@4ae00000/prm@6000/clocks/emu_dclk_div@194         9  N/ocp/l4@4ae00000/prm@6000/clocks/secure_32k_dclk_div@1c4          8  b/ocp/l4@4ae00000/prm@6000/clocks/clkoutmux0_clk_mux@158       8  u/ocp/l4@4ae00000/prm@6000/clocks/clkoutmux1_clk_mux@15c       8  /ocp/l4@4ae00000/prm@6000/clocks/clkoutmux2_clk_mux@160       9  /ocp/l4@4ae00000/prm@6000/clocks/custefuse_sys_gfclk_div          -  /ocp/l4@4ae00000/prm@6000/clocks/eve_clk@180          7  /ocp/l4@4ae00000/prm@6000/clocks/hdmi_dpll_clk_mux@164        -  /ocp/l4@4ae00000/prm@6000/clocks/mlb_clk@134          .  /ocp/l4@4ae00000/prm@6000/clocks/mlbp_clk@130         ;  /ocp/l4@4ae00000/prm@6000/clocks/per_abe_x1_gfclk2_div@138        7  /ocp/l4@4ae00000/prm@6000/clocks/timer_sys_clk_div@144        9  /ocp/l4@4ae00000/prm@6000/clocks/video1_dpll_clk_mux@168          9  /ocp/l4@4ae00000/prm@6000/clocks/video2_dpll_clk_mux@16c          6  ./ocp/l4@4ae00000/prm@6000/clocks/wkupaon_iclk_mux@108         '  ?/ocp/l4@4ae00000/prm@6000/clockdomains        *  P/ocp/l4@4ae00000/prm@6000/wkupaon_cm@1800         1  [/ocp/l4@4ae00000/prm@6000/wkupaon_cm@1800/clk@20            k/ocp/l4@4ae00000/scm_conf@c000          t/ocp/axi@0/pcie@51000000          .  }/ocp/axi@0/pcie@51000000/interrupt-controller           /ocp/axi@0/pcie_ep@51000000         /ocp/axi@1/pcie@51800000          .  /ocp/axi@1/pcie@51800000/interrupt-controller           /ocp/ocmcram@40300000           /ocp/ocmcram@40400000           /ocp/ocmcram@40500000           /ocp/bandgap@4a0021e0           /ocp/dsp_system@40d00000            /ocp/padconf@4844a000         ,  /ocp/padconf@4844a000/mmc1_iodelay_ddr_conf       /  /ocp/padconf@4844a000/mmc1_iodelay_sdr104_conf        .  /ocp/padconf@4844a000/mmc2_iodelay_hs200_conf         0  -/ocp/padconf@4844a000/mmc3_iodelay_manual1_conf       .  G/ocp/padconf@4844a000/mmc3_iodelay_sdr50_conf         0  _/ocp/padconf@4844a000/mmc4_iodelay_manual1_conf       0  y/ocp/padconf@4844a000/mmc4_iodelay_default_conf         /ocp/dma-controller@4a056000            /ocp/edma@43300000          /ocp/tptc@43400000          /ocp/tptc@43500000          /ocp/gpio@4ae10000          /ocp/gpio@48055000          /ocp/gpio@48057000          /ocp/gpio@48059000          /ocp/gpio@4805b000          /ocp/gpio@4805d000          /ocp/gpio@48051000          /ocp/gpio@48053000          /ocp/serial@4806a000            /ocp/serial@4806c000            /ocp/serial@48020000            /ocp/serial@4806e000            /ocp/serial@48066000             /ocp/serial@48068000             /ocp/serial@48420000             /ocp/serial@48422000             /ocp/serial@48424000             /ocp/serial@4ae2b000              /ocp/mailbox@4a0f4000            )/ocp/mailbox@4883a000            2/ocp/mailbox@4883c000            ;/ocp/mailbox@4883e000            D/ocp/mailbox@48840000         &   M/ocp/mailbox@48840000/mbox_ipu1_ipc3x         &   ]/ocp/mailbox@48840000/mbox_dsp1_ipc3x            m/ocp/mailbox@48842000         &   v/ocp/mailbox@48842000/mbox_ipu2_ipc3x         &   /ocp/mailbox@48842000/mbox_dsp2_ipc3x            /ocp/mailbox@48844000            /ocp/mailbox@48846000            /ocp/mailbox@4885e000            /ocp/mailbox@48860000            /ocp/mailbox@48862000            /ocp/mailbox@48864000            /ocp/mailbox@48802000            /ocp/timer@4ae18000          /ocp/timer@48032000          /ocp/timer@48034000          /ocp/timer@48036000          /ocp/timer@48820000          /ocp/timer@48822000         !/ocp/timer@48824000         !
/ocp/timer@48826000         !/ocp/timer@4803e000         !/ocp/timer@48086000         ! /ocp/timer@48088000         !(/ocp/timer@4ae20000         !0/ocp/timer@48828000         !8/ocp/timer@4882a000         !@/ocp/timer@4882c000         !H/ocp/timer@4882e000         !P/ocp/wdt@4ae14000           !U/ocp/spinlock@4a0f6000          !`/ocp/ipu@58820000           !e/ocp/ipu@55020000           !j/ocp/dsp@40800000            N/ocp/i2c@48070000           !o/ocp/i2c@48070000/tps65917@58         7  !x/ocp/i2c@48070000/tps65917@58/tps65917_pmic/regulators        >  !/ocp/i2c@48070000/tps65917@58/tps65917_pmic/regulators/smps12         =  !/ocp/i2c@48070000/tps65917@58/tps65917_pmic/regulators/smps3          =  !/ocp/i2c@48070000/tps65917@58/tps65917_pmic/regulators/smps4          =  !/ocp/i2c@48070000/tps65917@58/tps65917_pmic/regulators/smps5          <  !/ocp/i2c@48070000/tps65917@58/tps65917_pmic/regulators/ldo1       <  !/ocp/i2c@48070000/tps65917@58/tps65917_pmic/regulators/ldo2       <  !/ocp/i2c@48070000/tps65917@58/tps65917_pmic/regulators/ldo3       <  !/ocp/i2c@48070000/tps65917@58/tps65917_pmic/regulators/ldo5       <  !/ocp/i2c@48070000/tps65917@58/tps65917_pmic/regulators/ldo4         !/ocp/i2c@48070000/lp87565@60          (  !/ocp/i2c@48070000/lp87565@60/regulators       /  !/ocp/i2c@48070000/lp87565@60/regulators/buck10        /  !/ocp/i2c@48070000/lp87565@60/regulators/buck23          " /ocp/i2c@48070000/pcf8757@20            "/ocp/i2c@48070000/pcf8757@21            "/ocp/i2c@48070000/pcf8575@26          #  "/ocp/i2c@48070000/tlv320aic3106@19           S/ocp/i2c@48072000            X/ocp/i2c@48060000            ]/ocp/i2c@4807a000           "+/ocp/i2c@4807c000         +  "0/ocp/i2c@4807c000/ov10633@37/port/endpoint          ":/ocp/mmc@4809c000           "?/ocp/1w@480b2000            "F/ocp/mmc@480b4000           "K/ocp/mmc@480ad000           "P/ocp/mmc@480d1000           "U/ocp/mmu@40d01000           "_/ocp/mmu@40d02000           "i/ocp/mmu@58882000           "r/ocp/mmu@55082000           "{/ocp/pruss-soc-bus@4b226004       +  "/ocp/pruss-soc-bus@4b226004/pruss@4b200000        =  "/ocp/pruss-soc-bus@4b226004/pruss@4b200000/memories@4b200000          8  "/ocp/pruss-soc-bus@4b226004/pruss@4b200000/cfg@4b226000       8  "/ocp/pruss-soc-bus@4b226004/pruss@4b200000/iep@4b22e000       ;  "/ocp/pruss-soc-bus@4b226004/pruss@4b200000/mii-rt@4b232000        I  "/ocp/pruss-soc-bus@4b226004/pruss@4b200000/interrupt-controller@4b220000          8  "/ocp/pruss-soc-bus@4b226004/pruss@4b200000/pru@4b234000       8  "/ocp/pruss-soc-bus@4b226004/pruss@4b200000/pru@4b238000       9  "/ocp/pruss-soc-bus@4b226004/pruss@4b200000/mdio@4b232400            "/ocp/pruss-soc-bus@4b2a6004       +  "/ocp/pruss-soc-bus@4b2a6004/pruss@4b280000        =  "/ocp/pruss-soc-bus@4b2a6004/pruss@4b280000/memories@4b280000          8  #/ocp/pruss-soc-bus@4b2a6004/pruss@4b280000/cfg@4b2a6000       8  #/ocp/pruss-soc-bus@4b2a6004/pruss@4b280000/iep@4b2ae000       ;  #/ocp/pruss-soc-bus@4b2a6004/pruss@4b280000/mii-rt@4b2b2000        I  #+/ocp/pruss-soc-bus@4b2a6004/pruss@4b280000/interrupt-controller@4b2a0000          8  #7/ocp/pruss-soc-bus@4b2a6004/pruss@4b280000/pru@4b2b4000       8  #>/ocp/pruss-soc-bus@4b2a6004/pruss@4b280000/pru@4b2b8000       9  #E/ocp/pruss-soc-bus@4b2a6004/pruss@4b280000/mdio@4b2b2400            #Q/ocp/regulator-abb-mpu          #Y/ocp/regulator-abb-ivahd            #c/ocp/regulator-abb-dspeve           #n/ocp/regulator-abb-gpu          #v/ocp/spi@48098000           #}/ocp/spi@4809a000           #/ocp/spi@480b8000           #/ocp/spi@480ba000           #/ocp/qspi@4b300000        #  #/ocp/ocp2scp@4a090000/phy@4a096000        '  #/ocp/ocp2scp@4a090000/pciephy@4a094000        '  #/ocp/ocp2scp@4a090000/pciephy@4a095000          #/ocp/sata@4a141100          #/ocp/rtc@48838000         #  #/ocp/ocp2scp@4a080000/phy@4a084000        #  #/ocp/ocp2scp@4a080000/phy@4a085000        #  #/ocp/ocp2scp@4a080000/phy@4a084400          #/ocp/omap_dwc3_1@48880000         '  #/ocp/omap_dwc3_1@48880000/usb@48890000          #/ocp/omap_dwc3_2@488c0000         '  #/ocp/omap_dwc3_2@488c0000/usb@488d0000          #/ocp/omap_dwc3_3@48900000         '  $	/ocp/omap_dwc3_3@48900000/usb@48910000          $/ocp/elm@48078000           $/ocp/gpmc@50000000          $/ocp/atl@4843c000           $/ocp/mcasp@48460000         $"/ocp/mcasp@48464000         $)/ocp/mcasp@48468000         $0/ocp/mcasp@4846c000         $7/ocp/mcasp@48470000         $>/ocp/mcasp@48474000         $E/ocp/mcasp@48478000         $L/ocp/mcasp@4847c000         $S/ocp/crossbar@4a002a48          &/ocp/ethernet@48484000        %  $`/ocp/ethernet@48484000/mdio@48485000          4  $m/ocp/ethernet@48484000/mdio@48485000/ethernet-phy@2       4  $w/ocp/ethernet@48484000/mdio@48485000/ethernet-phy@3       &  $/ocp/ethernet@48484000/slave@48480200         &  $/ocp/ethernet@48484000/slave@48480300         -  $/ocp/ethernet@48484000/cpsw-phy-sel@4a002554            $/ocp/can@4ae3c000           $/ocp/can@48480000           #r/ocp/gpu@56000000           $/ocp/bb2d@59000000          $/ocp/dss@58000000         #  "/ocp/dss@58000000/encoder@58060000        1  $/ocp/dss@58000000/encoder@58060000/port/endpoint            $/ocp/epwmss@4843e000          "  $/ocp/epwmss@4843e000/pwm@4843e200         #  $/ocp/epwmss@4843e000/ecap@4843e100          $/ocp/epwmss@48440000          "  $/ocp/epwmss@48440000/pwm@48440200         #  $/ocp/epwmss@48440000/ecap@48440100          $/ocp/epwmss@48442000          "  $/ocp/epwmss@48442000/pwm@48442200         #  $/ocp/epwmss@48442000/ecap@48442100          $/ocp/aes@4b500000           %/ocp/aes@4b700000           %	/ocp/des@480a5000           %/ocp/sham@53100000          %/ocp/rng@48090000           %/ocp/opp-supply@4a003b20            %%/ocp/vip@0x48970000       !  %*/ocp/vip@0x48970000/ports/port@0          !  %0/ocp/vip@0x48970000/ports/port@1          ,  %6/ocp/vip@0x48970000/ports/port@1/endpoint@0       !  %?/ocp/vip@0x48970000/ports/port@2          !  %E/ocp/vip@0x48970000/ports/port@3            %K/ocp/dsp_system@41500000            %W/ocp/omap_dwc3_4@48940000         '  %c/ocp/omap_dwc3_4@48940000/usb@48950000          %h/ocp/mmu@41501000           %r/ocp/mmu@41502000           %m/ocp/dsp@41000000           %|/ocp/vip@0x48990000       !  %/ocp/vip@0x48990000/ports/port@0          !  %/ocp/vip@0x48990000/ports/port@1          !  %/ocp/vip@0x48990000/ports/port@2          !  %/ocp/vip@0x48990000/ports/port@3            %/ocp/vip@0x489b0000       !  %/ocp/vip@0x489b0000/ports/port@0          !  %/ocp/vip@0x489b0000/ports/port@1            %/ocp/emif@4c000000        &  %/ocp/target-module@42c01900/mcan@1a00           %/ocp/cal@489b0000           %/ocp/cal@489b0000/ports/port@0          %/ocp/cal@489b0000/ports/port@1          %/thermal-zones          %/thermal-zones/cpu_thermal        !  %/thermal-zones/cpu_thermal/trips          +  %/thermal-zones/cpu_thermal/trips/cpu_alert        *  %/thermal-zones/cpu_thermal/trips/cpu_crit         (  &/thermal-zones/cpu_thermal/cooling-maps         &/thermal-zones/gpu_thermal        *  &/thermal-zones/gpu_thermal/trips/gpu_crit           &'/thermal-zones/core_thermal       ,  &4/thermal-zones/core_thermal/trips/core_crit         &>/thermal-zones/dspeve_thermal         0  &M/thermal-zones/dspeve_thermal/trips/dspeve_crit         &Y/thermal-zones/iva_thermal        *  &e/thermal-zones/iva_thermal/trips/iva_crit           &n/extcon_usb1            &z/extcon_usb2             /sound0         &/sound0/simple-audio-card,cpu           &/clk_ov10633_fixed        #  &/reserved-memory/ipu2_cma@95800000        #  &/reserved-memory/dsp1_cma@99000000        #  &/reserved-memory/ipu1_cma@9d000000        #  &/reserved-memory/dsp2_cma@9f000000          &/fixedregulator-vsys12v0            &/fixedregulator-vsys5v0         &/fixedregulator-vio_3v6         &/fixedregulator-vsys3v3         '/fixedregulator-vio_3v3         '
/fixedregulator-sd          '/fixedregulator-vio_1v8         '/fixedregulator-mmcwl           '*/fixedregulator-vtt         '4/fixedregulator-aic_dvdd            '=/connector          'C/connector/port/endpoint          	  'U/encoder            '_/encoder/ports/port@0/endpoint          'l/encoder/ports/port@1/endpoint           	#address-cells #size-cells compatible interrupt-parent model stdout-path i2c0 i2c1 i2c2 i2c3 i2c4 serial0 serial1 serial2 serial3 serial4 serial5 serial6 serial7 serial8 serial9 ethernet0 ethernet1 d_can0 d_can1 spi0 rproc0 rproc1 rproc2 rproc3 display0 sound0 sound1 interrupts interrupt-controller #interrupt-cells reg phandle device_type operating-points-v2 clocks clock-names clock-latency #cooling-cells vbb-supply vdd-supply syscon opp-shared opp-hz opp-microvolt opp-supported-hw opp-suspend ti,hwmods ranges interrupts-extended regulator-name regulator-min-microvolt regulator-max-microvolt #clock-cells ti,bit-shift ti,max-div ti,latch-bit assigned-clocks assigned-clock-rates assigned-clock-parents #pinctrl-cells pinctrl-single,register-width pinctrl-single,function-mask pinctrl-single,pins #syscon-cells #dma-cells dma-requests ti,dma-safe-map dma-masters clock-frequency clock-mult clock-div ti,autoidle-shift ti,index-starts-at-one ti,invert-autoidle-bit ti,index-power-of-two ti,dividers reg-names bus-range num-lanes linux,pci-domain phys phy-names ti,syscon-lane-sel interrupt-map-mask interrupt-map status num-ib-windows num-ob-windows ti,syscon-unaligned-access #thermal-sensor-cells pinctrl-pin-array dma-channels interrupt-names ti,tptcs gpio-controller #gpio-cells dmas dma-names #mbox-cells ti,mbox-num-users ti,mbox-num-fifos ti,mbox-tx ti,mbox-rx ti,timer-alwon ti,timer-secure #hwlock-cells iommus ti,rproc-standby-info mboxes timers watchdog-timers memory-region syscon-bootreg ti,system-power-controller ti,palmas-override-powerhold smps12-in-supply smps3-in-supply smps4-in-supply smps5-in-supply ldo1-in-supply ldo2-in-supply ldo3-in-supply ldo4-in-supply ldo5-in-supply regulator-always-on regulator-boot-on regulator-allow-bypass wakeup-source ti,palmas-long-press-seconds buck10-in-supply buck23-in-supply gpio-hog gpios output-low line-name #sound-dai-cells adc-settle-ms ai3x-micbias-vg AVDD-supply IOVDD-supply DRVDD-supply DVDD-supply mux-gpios remote-endpoint hsync-active vsync-active pclk-sample pbias-supply max-frequency mmc-ddr-1_8v mmc-ddr-3_3v vmmc-supply vqmmc-supply bus-width cd-gpios pinctrl-names pinctrl-0 pinctrl-1 sdhci-caps-mask mmc-hs200-1_8v non-removable pinctrl-2 pinctrl-3 cap-power-off-card keep-power-in-suspend #iommu-cells ti,syscon-mmuconfig ti,iommu-bus-err-back firmware-name bus_freq ti,settling-time ti,clock-cycles ti,tranxdone-status-mask ti,ldovbb-override-mask ti,ldovbb-vset-mask ti,abb_info ti,spi-num-cs syscon-chipselects spi-max-frequency spi-tx-bus-width spi-rx-bus-width label syscon-phy-power syscon-pllreset #phy-cells syscon-pcs ports-implemented phy-supply ti,sysc-mask ti,sysc-sidle utmi-mode extcon maximum-speed dr_mode snps,dis_u3_susphy_quirk snps,dis_u2_susphy_quirk snps,dis_metastability_quirk gpmc,num-cs gpmc,num-waitpins ti,provided-clocks bws aws op-mode tdm-slots serial-dir tx-num-evt rx-num-evt ti,max-irqs ti,max-crossbar-sources ti,reg-size ti,irqs-reserved ti,irqs-skip ti,irqs-safe-map cpdma_channels ale_entries bd_ram_size mac_control slaves active_slave cpts_clock_mult cpts_clock_shift ti,no-idle dual_emac ti,rx-internal-delay ti,tx-internal-delay ti,fifo-depth ti,min-output-impedance ti,dp83867-rxctrl-strap-quirk mac-address phy_id phy-mode dual_emac_res_vlan syscon-raminit syscon-pll-ctrl vdda_video-supply syscon-pol vdda-supply #pwm-cells ti,efuse-settings ti,absolute-max-voltage-uv slave-mode ti,syss-mask bosch,mram-cfg max-bitrate syscon-camerrx polling-delay-passive polling-delay thermal-sensors coefficients temperature hysteresis trip cooling-device id-gpio vbus-gpio simple-audio-card,name simple-audio-card,widgets simple-audio-card,routing simple-audio-card,format simple-audio-card,bitclock-master simple-audio-card,frame-master simple-audio-card,bitclock-inversion sound-dai system-clock-frequency default-state autorepeat linux,code reusable vin-supply enable-active-high startup-delay-us gic wakeupgen cpu0 cpu0_opp_table l4_cfg scm scm_conf pbias_regulator pbias_mmc_reg scm_conf_clocks dss_deshdcp_clk ehrpwm0_tbclk ehrpwm1_tbclk ehrpwm2_tbclk sys_32k_ck dpll_gmac_h14x2_ctrl_ck dpll_gmac_h14x2_ctrl_mux_ck mcan_clk dra7_pmx_core mmc1_pins_default mmc1_pins_hs mmc1_pins_sdr50 mmc1_pins_ddr50 mmc2_pins_default mmc2_pins_hs200 mmc3_pins_default mmc4_pins_hs scm_conf1 scm_conf_pcie sdma_xbar edma_xbar cm_core_aon cm_core_aon_clocks atl_clkin0_ck atl_clkin1_ck atl_clkin2_ck atl_clkin3_ck hdmi_clkin_ck mlb_clkin_ck mlbp_clkin_ck pciesref_acs_clk_ck ref_clkin0_ck ref_clkin1_ck ref_clkin2_ck ref_clkin3_ck rmii_clk_ck sdvenc_clkin_ck secure_32k_clk_src_ck sys_clk32_crystal_ck sys_clk32_pseudo_ck virt_12000000_ck virt_13000000_ck virt_16800000_ck virt_19200000_ck virt_20000000_ck virt_26000000_ck virt_27000000_ck virt_38400000_ck sys_clkin2 usb_otg_clkin_ck video1_clkin_ck video1_m2_clkin_ck video2_clkin_ck video2_m2_clkin_ck dpll_abe_ck dpll_abe_x2_ck dpll_abe_m2x2_ck abe_clk dpll_abe_m2_ck dpll_abe_m3x2_ck dpll_core_byp_mux dpll_core_ck dpll_core_x2_ck dpll_core_h12x2_ck mpu_dpll_hs_clk_div dpll_mpu_ck dpll_mpu_m2_ck mpu_dclk_div dsp_dpll_hs_clk_div dpll_dsp_byp_mux dpll_dsp_ck dpll_dsp_m2_ck iva_dpll_hs_clk_div dpll_iva_byp_mux dpll_iva_ck dpll_iva_m2_ck iva_dclk dpll_gpu_byp_mux dpll_gpu_ck dpll_gpu_m2_ck dpll_core_m2_ck core_dpll_out_dclk_div dpll_ddr_byp_mux dpll_ddr_ck dpll_ddr_m2_ck dpll_gmac_byp_mux dpll_gmac_ck dpll_gmac_m2_ck video2_dclk_div video1_dclk_div hdmi_dclk_div per_dpll_hs_clk_div usb_dpll_hs_clk_div eve_dpll_hs_clk_div dpll_eve_byp_mux dpll_eve_ck dpll_eve_m2_ck eve_dclk_div dpll_core_h13x2_ck dpll_core_h14x2_ck dpll_core_h22x2_ck dpll_core_h23x2_ck dpll_core_h24x2_ck dpll_ddr_x2_ck dpll_ddr_h11x2_ck dpll_dsp_x2_ck dpll_dsp_m3x2_ck dpll_gmac_x2_ck dpll_gmac_h11x2_ck dpll_gmac_h12x2_ck dpll_gmac_h13x2_ck dpll_gmac_m3x2_ck gmii_m_clk_div hdmi_clk2_div hdmi_div_clk l3_iclk_div l4_root_clk_div video1_clk2_div video1_div_clk video2_clk2_div video2_div_clk dummy_ck cm_core_aon_clockdomains mpu_cm mpu_clkctrl dsp1_cm dsp1_clkctrl ipu1_cm ipu1_clkctrl ipu_cm ipu_clkctrl dsp2_cm dsp2_clkctrl rtc_cm rtc_clkctrl cm_core cm_core_clocks dpll_pcie_ref_ck dpll_pcie_ref_m2ldo_ck apll_pcie_in_clk_mux apll_pcie_ck optfclk_pciephy_div apll_pcie_clkvcoldo apll_pcie_clkvcoldo_div apll_pcie_m2_ck dpll_per_byp_mux dpll_per_ck dpll_per_m2_ck func_96m_aon_dclk_div dpll_usb_byp_mux dpll_usb_ck dpll_usb_m2_ck dpll_pcie_ref_m2_ck dpll_per_x2_ck dpll_per_h11x2_ck dpll_per_h12x2_ck dpll_per_h13x2_ck dpll_per_h14x2_ck dpll_per_m2x2_ck dpll_usb_clkdcoldo func_128m_clk func_12m_fclk func_24m_clk func_48m_fclk func_96m_fclk l3init_60m_fclk clkout2_clk l3init_960m_gfclk usb_phy1_always_on_clk32k usb_phy2_always_on_clk32k usb_phy3_always_on_clk32k gpu_core_gclk_mux gpu_hyd_gclk_mux l3instr_ts_gclk_div vip1_gclk_mux vip2_gclk_mux vip3_gclk_mux cm_core_clockdomains coreaon_clkdm coreaon_cm coreaon_clkctrl l3main1_cm l3main1_clkctrl ipu2_cm ipu2_clkctrl dma_cm dma_clkctrl emif_cm emif_clkctrl atl_cm atl_clkctrl l4cfg_cm l4cfg_clkctrl l3instr_cm l3instr_clkctrl dss_cm dss_clkctrl l3init_cm l3init_clkctrl l4per_cm l4per_clkctrl l4_wkup counter32k prm prm_clocks sys_clkin1 abe_dpll_sys_clk_mux abe_dpll_bypass_clk_mux abe_dpll_clk_mux abe_24m_fclk aess_fclk abe_giclk_div abe_lp_clk_div abe_sys_clk_div adc_gfclk_mux sys_clk1_dclk_div sys_clk2_dclk_div per_abe_x1_dclk_div dsp_gclk_div gpu_dclk emif_phy_dclk_div gmac_250m_dclk_div gmac_main_clk l3init_480m_dclk_div usb_otg_dclk_div sata_dclk_div pcie2_dclk_div pcie_dclk_div emu_dclk_div secure_32k_dclk_div clkoutmux0_clk_mux clkoutmux1_clk_mux clkoutmux2_clk_mux custefuse_sys_gfclk_div eve_clk hdmi_dpll_clk_mux mlb_clk mlbp_clk per_abe_x1_gfclk2_div timer_sys_clk_div video1_dpll_clk_mux video2_dpll_clk_mux wkupaon_iclk_mux prm_clockdomains wkupaon_cm wkupaon_clkctrl scm_wkup pcie1_rc pcie1_intc pcie1_ep pcie2_rc pcie2_intc ocmcram1 ocmcram2 ocmcram3 bandgap dsp1_system dra7_iodelay_core mmc1_iodelay_ddr_conf mmc1_iodelay_sdr104_conf mmc2_iodelay_hs200_conf mmc3_iodelay_manual1_conf mmc3_iodelay_sdr50_conf mmc4_iodelay_manual1_conf mmc4_iodelay_default_conf sdma edma edma_tptc0 edma_tptc1 gpio1 gpio2 gpio3 gpio4 gpio5 gpio6 gpio7 gpio8 uart1 uart2 uart3 uart4 uart5 uart6 uart7 uart8 uart9 uart10 mailbox1 mailbox2 mailbox3 mailbox4 mailbox5 mbox_ipu1_ipc3x mbox_dsp1_ipc3x mailbox6 mbox_ipu2_ipc3x mbox_dsp2_ipc3x mailbox7 mailbox8 mailbox9 mailbox10 mailbox11 mailbox12 mailbox13 timer1 timer2 timer3 timer4 timer5 timer6 timer7 timer8 timer9 timer10 timer11 timer12 timer13 timer14 timer15 timer16 wdt2 hwspinlock ipu1 ipu2 dsp1 tps65917 tps65917_regulators smps12_reg smps3_reg smps4_reg smps5_reg ldo1_reg ldo2_reg ldo3_reg ldo5_reg ldo4_reg lp87565 buck10_reg buck23_reg pcf_lcd pcf_gpio_21 pcf_hdmi tlv320aic3106 i2c5 onboardLI mmc1 hdqw1w mmc2 mmc3 mmc4 mmu0_dsp1 mmu1_dsp1 mmu_ipu1 mmu_ipu2 pruss_soc_bus1 pruss1 pruss1_mem pruss1_cfg pruss1_iep pruss1_mii_rt pruss1_intc pru1_0 pru1_1 pruss1_mdio pruss_soc_bus2 pruss2 pruss2_mem pruss2_cfg pruss2_iep pruss2_mii_rt pruss2_intc pru2_0 pru2_1 pruss2_mdio abb_mpu abb_ivahd abb_dspeve abb_gpu mcspi1 mcspi2 mcspi3 mcspi4 qspi sata_phy pcie1_phy pcie2_phy sata rtc usb2_phy1 usb2_phy2 usb3_phy1 omap_dwc3_1 usb1 omap_dwc3_2 usb2 omap_dwc3_3 usb3 elm gpmc atl mcasp1 mcasp2 mcasp3 mcasp4 mcasp5 mcasp6 mcasp7 mcasp8 crossbar_mpu davinci_mdio dp83867_0 dp83867_1 cpsw_emac0 cpsw_emac1 phy_sel dcan1 dcan2 bb2d dss hdmi_out epwmss0 ehrpwm0 ecap0 epwmss1 ehrpwm1 ecap1 epwmss2 ehrpwm2 ecap2 aes1 aes2 des sham rng opp_supply_mpu vip1 vin1a vin2a vin2a_ep vin1b vin2b dsp2_system omap_dwc3_4 usb4 mmu0_dsp2 mmu1_dsp2 vip2 vin3a vin4a vin3b vin4b vip3 vin5a vin6a emif1 m_can0 cal csi2_0 csi2_1 thermal_zones cpu_thermal cpu_trips cpu_alert0 cpu_crit cpu_cooling_maps gpu_thermal gpu_crit core_thermal core_crit dspeve_thermal dspeve_crit iva_thermal iva_crit extcon_usb1 extcon_usb2 sound0_master clk_ov10633_fixed ipu2_cma_pool dsp1_cma_pool ipu1_cma_pool dsp2_cma_pool vsys_12v0 vsys_5v0 vio_3v6 vsys_3v3 vio_3v3 vio_3v3_sd vio_1v8 vmmcwl_fixed vtt_fixed aic_dvdd hdmi0 hdmi_connector_in tpd12s015 tpd12s015_in tpd12s015_out display1 digital ddc-i2c-bus hpd-gpios data-lines output-high tfp410 tfp410_in tfp410_out dvi0 dvi_connector_in dpi_out pcf_tfp 